Curtis Beecher Ward

US Patent:

20040265748, Dec 30, 2004

Filed:

Jun 30, 2003

Appl. No.:

10/609926

Inventors:

Robert Bristol - Portland OR, US
Heidi Cao - Portland OR, US
Robert Meagley - Hillsboro OR, US
Bryan Rice - Hillsboro OR, US
Curtis Ward - Hillsboro OR, US

International Classification:

G03F007/00

US Classification:

430/313000, 430/015000, 430/316000, 430/394000

Abstract:

A method of forming a device feature using an extreme ultraviolet (EUV) imaging layer (or a sub-deep ultraviolet imaging layer) and one or more other masks layers. The method includes forming a device feature layer; forming a photoresist layer over the device feature layer; forming a contact mask layer (CML) over the photoresist layer; forming an extreme ultraviolet (EUV) imaging layer over the CML; forming a first opening through the EUV imaging layer to expose a first underlying region of the CML; forming a second opening through the CML to expose a second underlying region of the photoresist layer, wherein the second opening is situated directly below the first opening; forming a third opening through the photoresist layer to expose a third underlying region of the device feature layer, wherein the third opening is situated directly below the second opening; forming a fourth opening through the device feature material layer, wherein the fourth opening is situated directly below the third opening.

US Patent:

20050148180, Jul 7, 2005

Filed:

Dec 30, 2003

Appl. No.:

10/750200

Inventors:

Swaminathan Sivakumar - Portland OR, US
Curtis Ward - Hillsboro OR, US
Timothy Hehr - Portland OR, US
Mark Fradkin - Portland OR, US

International Classification:

H01L021/302
H01L021/461

US Classification:

438689000

Abstract:

The present invention relates to exposing a bond pad on a substrate. A bond pad is formed over a silicon substrate with the subsequent formation of a dielectric over the bond pad. A patterned resist is formed, and at least opening is processed to form a sloped sidewall profile. The sloped sidewall profile is subsequently etched and transferred to the dielectric layer, exposing the bond pad.

US Patent:

20050263899, Dec 1, 2005

Filed:

Aug 11, 2005

Appl. No.:

11/202462

Inventors:

Swaminathan Sivakumar - Portland OR, US
Curtis W. Ward - Hillsboro OR, US
Timothy L. Hehr - Portland OR, US
Mark A. Fradkin - Portland OR, US

International Classification:

H01L023/04

US Classification:

257758000

Abstract:

The present invention relates to exposing a bond pad on a substrate. A bond pad is formed over a silicon substrate with the subsequent formation of a dielectric over the bond pad. A patterned resist is formed, and at least opening is processed to form a sloped sidewall profile. The sloped sidewall profile is subsequently etched and transferred to the dielectric layer, exposing the bond pad.

US Patent:

20220262722, Aug 18, 2022

Filed:

May 2, 2022

Appl. No.:

17/735006

Inventors:

- Santa Clara CA, US
Robert L. BRISTOL - Portland OR, US
Kevin L. LIN - Beaverton OR, US
Florian GSTREIN - Portland OR, US
James M. BLACKWELL - Portland OR, US
Marie KRYSAK - Portland OR, US
Manish CHANDHOK - Beaverton OR, US
Paul A. NYHUS - Portland OR, US
Charles H. WALLACE - Portland OR, US
Curtis W. WARD - Hillsboro OR, US
Swaminathan SIVAKUMAR - Beaverton OR, US
Elliot N. TAN - Portland OR, US

International Classification:

H01L 23/528
H01L 23/522
H01L 23/532
H01L 27/088
H01L 29/78

Abstract:

Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

US Patent:

20210249523, Aug 12, 2021

Filed:

Apr 16, 2021

Appl. No.:

17/233063

Inventors:

- Santa Clara CA, US
Byron HO - Hillsboro OR, US
Curtis W. WARD - Hillsboro OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

International Classification:

H01L 29/66
H01L 29/78
H01L 27/088
H01L 21/762
H01L 29/06
H01L 21/8234
H01L 21/768
H01L 23/522
H01L 23/532
H01L 29/165
H01L 29/417
H01L 21/033
H01L 21/28
H01L 21/285
H01L 21/308
H01L 21/311
H01L 21/8238
H01L 23/528
H01L 27/092
H01L 27/11
H01L 49/02
H01L 29/08
H01L 29/51
H01L 27/02
H01L 21/02
H01L 29/167

Abstract:

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

US Patent:

20210143051, May 13, 2021

Filed:

Jan 15, 2021

Appl. No.:

17/151083

Inventors:

- Santa Clara CA, US
Curtis WARD - Hillsboro OR, US
Heidi M. MEYER - Hillsboro OR, US
Tahir GHANI - Portland OR, US
Christopher P. AUTH - Portland OR, US

International Classification:

H01L 21/762
H01L 27/092
H01L 29/06
H01L 21/8238

Abstract:

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.

US Patent:

20210090990, Mar 25, 2021

Filed:

Sep 23, 2019

Appl. No.:

16/579077

Inventors:

- Santa Clara CA, US
Manish CHANDHOK - Beaverton OR, US
Richard E. SCHENKER - Portland OR, US
Florian GSTREIN - Portland OR, US
Leonard P. GULER - Hillsboro OR, US
Charles H. WALLACE - Portland OR, US
Paul A. NYHUS - Portland OR, US
Curtis WARD - Forest Grove OR, US
Mohit K. HARAN - Hillsboro OR, US
Reken PATEL - Portland OR, US

International Classification:

H01L 23/522
H01L 21/768
H01L 21/02
H01L 23/66

Abstract:

Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.

US Patent:

20210082800, Mar 18, 2021

Filed:

Dec 2, 2020

Appl. No.:

17/110215

Inventors:

- Santa Clara CA, US
Robert L. BRISTOL - Portland OR, US
Kevin L. LIN - Beaverton OR, US
Florian GSTREIN - Portland OR, US
James M. BLACKWELL - Portland OR, US
Marie KRYSAK - Portland OR, US
Manish CHANDHOK - Beaverton OR, US
Paul A. NYHUS - Portland OR, US
Charles H. WALLACE - Portland OR, US
Curtis W. WARD - Hillsboro OR, US
Swaminathan SIVAKUMAR - Beaverton OR, US
Elliot N. TAN - Portland OR, US

International Classification:

H01L 23/528
H01L 23/522
H01L 23/532
H01L 27/088
H01L 29/78

Abstract:

Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.