Cynthia Hsu

US Patent:

8472257, Jun 25, 2013

Filed:

Mar 24, 2011

Appl. No.:

13/071170

Inventors:

Yingda Dong - San Jose CA, US
Ken Oowada - Fujisawa, JP
Cynthia Hsu - Milpitas CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 16/10

US Classification:

36518519

Abstract:

A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V,. . . , V). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vamong the set by a predetermined margin. The overshoot of each memory cell when programmed past V, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.

US Patent:

8208310, Jun 26, 2012

Filed:

May 4, 2010

Appl. No.:

12/773701

Inventors:

Yingda Dong - San Jose CA, US
Yan Li - Milpitas CA, US
Cynthia Hsu - San Jose CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 16/06

US Classification:

36518522, 36518525, 36518521, 36518501

Abstract:

Channel coupling effects during verify and read of non-volatile storage are mitigated by matching the amount of channel coupling that occurs during read with channel coupling that occurred during verify. All bit lines may be read together during both verify and read. In one embodiment, first bias conditions are established on bit lines when verifying each of a plurality of programmed states. A separate set of first bias conditions may be established when verifying each state. Biasing a bit line may be based on the state to which a non-volatile storage elements on the bit line is being programmed. A separate set of second bias conditions are established for each state being read. The second bias conditions for a given state substantially match the first bias conditions for the given state.

US Patent:

20100329002, Dec 30, 2010

Filed:

Jun 24, 2009

Appl. No.:

12/490557

Inventors:

Yingda Dong - San Jose CA, US
Cynthia Hsu - San Jose CA, US

International Classification:

G11C 16/04

US Classification:

36518502, 36518519, 36518524

Abstract:

Program disturb is reduced in a non-volatile storage system during a programming operation by determining a susceptibility of a set of storage elements to program disturb and taking a corresponding precautionary measure, if needed, to reduce the likelihood of program disturb occurring. During programming of a lower page of data, a natural threshold voltage distribution of the set of storage elements is determined by tracking storage elements which are programmed to a particular state, and determining how many program pulses are need for a number N and a number N>N of the storage elements to reach the particular state. Temperature and word line position can also be used to determine the susceptibility to program disturb. A precautionary measure can involve using a higher pass voltage, or abandoning programming of an upper page of data or an entire block. In some cases, programming continues with no precautionary measure.

US Patent:

20120167100, Jun 28, 2012

Filed:

Dec 23, 2010

Appl. No.:

12/978001

Inventors:

Yan Li - Milpitas CA, US
Alon Marcu - Tel-Mond, IL
Cynthia Hsu - San Jose CA, US
Grishma Shah - San Jose CA, US
Cuong Trinh - Fremont CA, US
Mehrdad Mofidi - Fremont CA, US

International Classification:

G06F 9/46
G06F 3/00

US Classification:

718102, 710 19, 710 5

Abstract:

An external controller has greater control over control circuitry on a memory die in a non-volatile storage system. The external controller can issue a manual suspend command on a communication path which is constantly monitored by the control circuitry. In response, the control circuitry suspends a task immediately, with essentially no delay, or at a next acceptable point in the task. The external controller similarly has the ability to issue a manual resume command, which can be provided on the communication path when that path has a ready status. The control circuitry can also automatically suspend and resume a task. The external controller can cause a task to be suspended by issuing an illegal read command. The external controller can cause a suspended program task to be aborted by issuing a new program command.

US Patent:

20130155769, Jun 20, 2013

Filed:

Dec 16, 2011

Appl. No.:

13/329103

Inventors:

Yan Li - Milpitas CA, US
Cynthia Hsu - Fremont CA, US
Ken Oowada - Fujisawa, JP

International Classification:

G11C 16/10

US Classification:

36518503

Abstract:

A nonvolatile memory with a multi-pass programming scheme enables a page of multi-level memory cells to be programmed with reduced floating-gate to floating-gate perturbations (Yuping effect). The memory cells operate within a common threshold voltage range or window, which is partitioned into multiple bands to denote a series of increasingly programmed states. The series is divided into two halves, a lower set and a higher set. The memory cells are programmed in a first, coarse programming pass such that the memory cells of the page with target states from the higher set are programmed to a staging area near midway in the threshold window. In particular, they are programmed closer to their targeted destinations than previous schemes, without incurring much performance penalty. Subsequent passes will then complete the programming more quickly. Yuping effect is reduced since the threshold voltage change in subsequent passes are reduced.

US Patent:

20130279263, Oct 24, 2013

Filed:

Jun 24, 2013

Appl. No.:

13/925621

Inventors:

Ken Oowada - Fujisawa, JP
Cynthia Hsu - Milpitas CA, US

International Classification:

G11C 16/04

US Classification:

36518519

Abstract:

A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V, . . . , V). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vamong the set by a predetermined margin. The overshoot of each memory cell when programmed past V, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.

US Patent:

20210327520, Oct 21, 2021

Filed:

Apr 21, 2020

Appl. No.:

16/854030

Inventors:

- Addison TX, US
Deepanshu Dutta - San Jose CA, US
Ravi Kumar - Redwood City CA, US
Cynthia Hsu - San Jose CA, US

Assignee:

SanDisk Technologies LLC - Addison TX

International Classification:

G11C 16/34
G11C 16/10
G11C 16/26
G11C 16/24
G11C 16/08

Abstract:

A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.

US Patent:

20200126613, Apr 23, 2020

Filed:

Dec 17, 2019

Appl. No.:

16/717532

Inventors:

- Addison TX, US
Zhuojie Li - Newark CA, US
Henry Chin - Fremont CA, US
Cynthia Hsu - Milpitas CA, US

Assignee:

SANDISK TECHNOLOGIES LLC - Addison TX

International Classification:

G11C 11/56
G11C 16/08
G11C 29/12
G11C 16/26
G11C 16/34
G11C 16/04

Abstract:

An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.