Cynthia Revoredo Torres

US Patent:

7215150, May 8, 2007

Filed:

Jan 31, 2005

Appl. No.:

11/047427

Inventors:

Cynthia A. Torres - Austin TX, US
Lloyd P. Matthews - Buda TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03K 19/0175
H03K 3/00

US Classification:

326 83, 326 80, 326 81, 327112, 327333

Abstract:

A circuit implements a method to adjust input/output (I/O) characteristics of an I/O pad circuit () depending upon which value of an I/O supply voltage is used within a range of supply voltages. An I/O supply voltage being supplied to the pad circuit is detected by detecting () its value relative to a known reference (). Portions of the I/O pad circuit are selectively enabled in response to the detected I/O supply voltage. By selecting the ratio of P-channel and N-channel transistors, physical characteristics of the circuit are controlled. Examples of the controlled physical characteristics include slew rate, signal rise and fall times, and duty cycle control which is controlled by forcing all rising and falling edges to have a midpoint at the same point in time. Therefore a same I/O pad circuit may be optimally used in numerous applications regardless of the supply voltage value.

US Patent:

59461772, Aug 31, 1999

Filed:

Aug 17, 1998

Appl. No.:

9/134943

Inventors:

James Wesley Miller - Austin TX
Cynthia Ann Torres - Austin TX
Troy L. Cooper - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H02H 900

US Classification:

361 56

Abstract:

A circuit (100) ensures electrostatic discharge (ESD) protection during an ESD event. The ESD circuit (100) has a current shunting device (135), a RC trigger circuit (125) and a RC delay circuit (130). The shunting device (135) is connected between two IC power supply rails, and provides the primary current path for a positive ESD event referenced from one power supply rail (V. sub. DD 105) to the other (V. sub. ss 110). The trigger circuit (125) initially activates the shunting device into a low resistance conductive state in response to an ESD event. The RC delay circuit (130) serves to maintain the shunting device in the conductive state, initially produced by the trigger circuit (125), for the remaining duration of the ESD event. A large capacitor required to achieve the delay time in this RC circuit may be eliminated by utilizing the gate-to-body capacitance in the existing shunting device (135).

US Patent:

20170229444, Aug 10, 2017

Filed:

Feb 4, 2016

Appl. No.:

15/015492

Inventors:

- AUSTIN TX, US
Cynthia A. TORRES - Austin TX, US

International Classification:

H01L 27/02
H02H 9/04

Abstract:

Electrostatic discharge (ESD) protection circuitry in an integrated circuit is provided. The protection circuitry includes a trigger circuit coupled between a first power supply bus and a second power supply bus. A delay circuit is coupled to receive an output signal from the trigger circuit. The delay circuit includes a first inverter coupled to the input of the delay circuit and a feedback transistor having a control terminal coupled to the output of the delay circuit, a first current electrode coupled to the first power supply bus, and a second current electrode coupled to the output of the first inverter. A clamp driver circuit is coupled to the output of the delay circuit.

US Patent:

20140198415, Jul 17, 2014

Filed:

Jan 14, 2013

Appl. No.:

13/741341

Inventors:

- Dallas TX, US
Cynthia Ann Torres - Austin TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H02H 3/22

US Classification:

361 56

Abstract:

ESD protection apparatus disclosed herein include an ESD trigger circuit to sense the occurrence of an ESD event and an ESD discharge device to provide a low impedance path to ground through which to discharge energy associated with the ESD pulse. Some embodiments also include a VDD turn-on clamp to prevent the ESD discharge device from switching to a conductive state during a VDD power-on event. Some embodiments further include a VDD glitch clamp to prevent a switching pulse triggered by a transient disruption in the VDD supply from propagating to the ESD discharge device and causing the ESD discharge device to conduct in the absence of an ESD event.