Cynthia J Tran

US Patent:

20040078417, Apr 22, 2004

Filed:

Oct 22, 2002

Appl. No.:

10/278440

Inventors:

Sanjay Dubey - Sunnyvale CA, US
Yoganand Chillarige - Sunnyvale CA, US
Shivakumar Sompur - Sunnyvale CA, US
Ban Wong - Milpitas CA, US
Cynthia Tran - San Jose CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F007/50

US Classification:

708/706000

Abstract:

An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.