Daihyun Lim

US Patent:

8519761, Aug 27, 2013

Filed:

May 25, 2012

Appl. No.:

13/480573

Inventors:

Marcel A. Kossel - Reichenburg, CH
Daihyun Lim - West New York NJ, US
Pradeep Thiagarajan - Chapel Hill NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 5/12

US Classification:

327170

Abstract:

A slew rate control circuit generates a slew-rate controlled clock signal from an input clock signal based on a feedback control mechanism. The feedback control mechanism uses the input clock signal duty cycle characteristics as a reference for controlling and maintaining an optimum slew rate for the slew-rate controlled clock signal. By using the input clock signal as a reference, the slew-rate controlled clock signal is dynamically measured and periodically adjusted over each cycle of the input clock signal.

US Patent:

8638149, Jan 28, 2014

Filed:

Aug 6, 2012

Appl. No.:

13/567214

Inventors:

Marcel A. Kossel - Reichenburg, CH
Daihyun Lim - West New York NJ, US
Pradeep Thiagarajan - Chapel Hill NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 5/12

US Classification:

327170, 327108

Abstract:

Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.

US Patent:

20120025888, Feb 2, 2012

Filed:

Jul 29, 2010

Appl. No.:

12/845966

Inventors:

Marcel A. Kossel - Reichenburg, CH
Daihyun Lim - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/04

US Classification:

327299

Abstract:

A phase rotator includes a phase selector stage operative to receive a clock signal and output a first phase and a second phase of the clock signal, a slew rate control stage including a first pass gate circuit operative to control a slew rate of the first phase of the clock signal and a second pass gate circuit operative to control a slew rate of the second phase of the clock signal, and a phase blending stage operative to combine the first phase with the second phase of the clock signal and output a phase rotated signal.

US Patent:

20200393706, Dec 17, 2020

Filed:

Jun 13, 2019

Appl. No.:

16/439825

Inventors:

- New York NY, US
Abdelrahman Ahmed - Brooklyn NY, US
Daihyun Lim - Edgewater NJ, US
Alexander Rylyakov - Staten Island NY, US

International Classification:

G02F 1/01
G02F 1/225
H03F 3/45
H03G 3/30

Abstract:

Within a modulator driver, different blocks are employed, e.g. a buffer, one or more variable gain amplifiers (VGA), and a final driver stage. Each of these blocks has an optimum bias point for best performance; however, interconnecting the blocks requires sharing the DC bias points in their interface, which does not necessarily match the optimum performance bias point of each block.. Accordingly, a first offset feedback loop extending from reference points after a selected one of the blocks to an input of one of the blocks. The first offset feedback loop includes current sources capable of delivering a variable current to the input of the selected block in order to compensate any offset in an amplified differential input electrical signal measured at the reference points. A first bias feedback loop is also provided, including a current sinker for subtracting excess current introduced in the first offset compensation feedback loop.

US Patent:

20160322938, Nov 3, 2016

Filed:

Jul 13, 2016

Appl. No.:

15/209190

Inventors:

- Armonk NY, US
Daihyun Lim - Edgewater NJ, US
Pradeep Thiagarajan - Chapel Hill NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03B 27/00
H03K 5/14
H03K 3/03

Abstract:

The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.

US Patent:

20160173069, Jun 16, 2016

Filed:

Dec 15, 2015

Appl. No.:

14/969127

Inventors:

- Armonk NY, US
Daihyun Lim - Edgewater NJ, US
Pradeep Thiagarajan - Chapel Hill NC, US

International Classification:

H03K 3/03

Abstract:

The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.

US Patent:

20150070069, Mar 12, 2015

Filed:

Sep 11, 2013

Appl. No.:

14/024233

Inventors:

- Armonk NY, US
Daihyun LIM - West New York NJ, US
Pradeep THIAGARAJAN - Chapel Hill NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19/0185

US Classification:

327333

Abstract:

A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs.