Dale Steven Martin

US Patent:

6352912, Mar 5, 2002

Filed:

Mar 30, 2000

Appl. No.:

09/539527

Inventors:

Jeffrey Scott Brown - Middlesex VT
Stephen Scott Furkay - South Burlington VT
Dale Warner Martin - Hyde Park VT
James Albert Slinkman - Montpelier VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21265

US Classification:

438528, 438289, 438306

Abstract:

A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and drain of the FET. The germanium can be implanted prior to gate and source and drain formation, and reduces the reverse short channel effect normally seen in FETs. The short channel effect normally occurring in FETs is not negatively impacted by the germanium implant.

US Patent:

6486510, Nov 26, 2002

Filed:

Nov 12, 2001

Appl. No.:

10/054297

Inventors:

Jeffrey Scott Brown - Middlesex VT
Stephen Scott Furkay - South Burlington VT
Dale Warner Martin - Hyde Park VT
James Albert Slinkman - Montpelier VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 310288

US Classification:

257327, 257611, 257616

Abstract:

A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and drain of the FET. The germanium can be implanted prior to gate and source and drain formation, and reduces the reverse short channel effect normally seen in FETs. The short channel effect normally occurring in FETs is not negatively impacted by the germanium implant.

US Patent:

7157341, Jan 2, 2007

Filed:

Oct 1, 2004

Appl. No.:

10/711742

Inventors:

Dale W. Martin - Hyde Park VT, US
Steven M. Shank - Jericho VT, US
Michael C. Triplett - Colchester VT, US
Deborah A. Tucker - Westford VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336
H01L 21/8238

US Classification:

438303, 438258, 438211

Abstract:

A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in a top layer of the gate polysilicon layer, (d) etching away portions of the gate polysilicon layer and the gate dielectric layer so as to form a gate stack on the substrate, and (e) thermally oxidizing side walls of the gate stack with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer is formed at the same depth in the polysilicon material of the gate stack regardless of the doping concentration. Therefore, the n-type doped region of the gate stack has the same width as that of the undoped region of the gate stack.

US Patent:

7378712, May 27, 2008

Filed:

Aug 8, 2006

Appl. No.:

11/463039

Inventors:

Dale W. Martin - Hyde Park VT, US
Steven M. Shank - Jericho VT, US
Michael C. Triplett - Colchester VT, US
Deborah A. Tucker - Westford VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

US Classification:

257369, 257900, 257E2706

Abstract:

A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.

US Patent:

59267089, Jul 20, 1999

Filed:

May 20, 1997

Appl. No.:

8/859588

Inventors:

Dale W. Martin - Hyde Park VT

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H01L 218242

US Classification:

438241

Abstract:

The present invention is directed to a method of manufacturing an integrated circuit with two or more gate oxide thicknesses on the same wafer. The method includes the steps of growing a first oxide layer on a substrate, depositing a first polysilicon layer over the first oxide layer, applying a block mask, etching the first polysilicon layer, stripping the block mask, stripping the first oxide layer from the areas opened by the block mask, growing a second oxide layer, depositing a second polysilicon layer, and polishing the second polysilicon layer to remove the second polysilicon layer from everywhere except the areas opened by the block mask. If desired, a polish stop layer may be deposited after depositing the first polysilicon layer. Threshold implants may also be made after the block mask is stripped. Finally, polysilicon shapes may be added to the boundary areas opened by the block mask to help eliminate foreign material problems.