Dale Alan Morris

US Patent:

6438682, Aug 20, 2002

Filed:

Oct 12, 1998

Appl. No.:

09/169866

Inventors:

Dale Morris - Menlo Park CA
Mircea Poplingher - Campbell CA
Tse-Yu Yeh - Milpitas CA
Michael P. Corwin - Palo Alto CA
Wenliang Chen - Sunnyvale CA

Assignee:

Intel Corporation - Santa CA

International Classification:

G06F 932

US Classification:

712241

Abstract:

A loop branch prediction system is provided to predict a final iteration of a loop and resteer an associated fetch module to an appropriate target address. The loop prediction system includes a counter and an end of loop (EOL) module. In one mode, the counter tracks loop branches in process. When a termination condition is detected, the counter switches to a second mode to track the number of loop branches still to be issued. The EOL module compares the number of loop branches still to be issued with one or more threshold values and generates a resteer signal when a match is detected.

US Patent:

6505296, Jan 7, 2003

Filed:

Mar 8, 2000

Appl. No.:

09/521160

Inventors:

Dale C. Morris - Menlo Park CA
Jonathan K. Ross - Woodinville WA
James O. Hays - San Jose CA
Jerome C. Huck - Palo Alto CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 942

US Classification:

712244, 710261, 710269

Abstract:

A computer system includes a processor for executing a program and an interruption handler from a memory. The processor includes an instruction pointer indicating a memory location of a current executing instruction. The processor executes a trampoline check instruction in the program which tests a condition and if the condition is true, causes an interruption and supplies an address displacement. The interruption handler responds to the interruption and restarts execution of the program at a restart point indicating a memory location of a special handler in the program. The restart point is a sum of the address displacement and a value of the instruction pointer at the time of the interruption. If the condition is false, normal control flow of the program is continued.

US Patent:

6550001, Apr 15, 2003

Filed:

Oct 30, 1998

Appl. No.:

09/183156

Inventors:

Michael P. Corwin - Sunnyvale CA
Dale Calvin Morris - Menlo Park CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

712216

Abstract:

An apparatus is provided for detecting instruction ordering dependencies. The apparatus includes a plurality of address comparators. Each comparator including a first input adapted to receive a first operand address from one of a plurality of instructions; a second input adapted to receive a second operand address from a second one of a plurality of instructions; and an output to transmit a logic signal responsive to a match between the first and second operand addresses. The address comparators receive the first operand address from a respective, different ones of the plurality of instructions; and a hardware structure to receive the match indications from the address comparators and to indicate a dependency responsive to the match indications from a first one and a second one of the address comparators. A method is provided for detecting instruction dependencies. The method includes receiving first and second pluralities of operand addresses that correspond to first and second pluralities of operands of instructions, and selecting ones of the first and second pluralities of operands.

US Patent:

6611910, Aug 26, 2003

Filed:

Oct 12, 1998

Appl. No.:

09/169868

Inventors:

Harshvardhan Sharangpani - Santa Clara CA
Tse-Yu Yeh - Milpitas CA
Michael Paul Corwin - Palo Alto CA
Millind Mittal - Palo Alto CA
Kent G. Fielden - Sunnyvale CA
Dale Morris - Steamboat Springs CO
Rajiv Gupta - Los Altos CA
Michael Schlansker - Los Altos CA
Mircea Poplingher - Palo Alto CA

Assignee:

Idea Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

712237, 709238

Abstract:

A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

US Patent:

6631460, Oct 7, 2003

Filed:

Apr 27, 2000

Appl. No.:

09/559508

Inventors:

Dale C. Morris - Menlo Park CA
William R. Bry - Saratoga CA
Alan H. Karp - Palo Alto CA
William Chen - Sunnyvale CA

Assignee:

Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA

International Classification:

G06T 930

US Classification:

712217, 712228, 712216

Abstract:

A computer system includes physical registers holding data for compiled programs and a portion of the physical registers form a register stack which wraps around when full. An N-bit current wraparound count state tracks physical register remapping events which cause the register stack to wraparound or unwrap. An advanced load address table (ALAT) has entries corresponding to load instructions, each entry has at least one memory range field defining a range of memory locations accessed by a corresponding load instruction, a physical register number field corresponding to a physical register accessed in the corresponding load instruction, and an N-bit register wraparound field which corresponds to the N-bit current wraparound count state for the corresponding load instruction. A check instruction accesses the ALAT to determine whether a store instruction and an advanced load instruction, which is scheduled before the store instruction, potentially accessed a common memory location. After the execution of the store instruction, an absence of an entry corresponding to the load instruction in the ALAT indicates that a common memory location may have been accessed by the store and load instructions.

US Patent:

6799263, Sep 28, 2004

Filed:

Oct 28, 1999

Appl. No.:

09/430361

Inventors:

Dale C. Morris - Menlo Park CA
James R. Callister - San Jose CA
Stephen R. Undy - Ft. Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 940

US Classification:

712207, 712235, 712237, 712239, 711119

Abstract:

A method for prefetching instructions into cache memory using a prefetch instruction. The prefetch instruction contains a target field, a count field, a cache level field, a flush field, and a trace field. The target field specifies the address at which prefetching begins. The count field specifies the number of instructions to prefetch. The flush field indicates whether earlier prefetches should be discarded and whether in-progress prefetches should be aborted. The level field specifies the level of the cache into which the instructions should be prefetched. The trace field establishes a trace vector that can be used to determine whether the prefetching operation specified by the operation should be aborted. The prefetch instruction may be used in conjunction with a branch predict instruction to prefetch a branch of instructions that is not predicted.

US Patent:

6813627, Nov 2, 2004

Filed:

Jul 31, 2001

Appl. No.:

09/920250

Inventors:

James M. Hull - Saratoga CA
Dale C. Morris - Steamboat Springs CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 752

US Classification:

708620, 708518

Abstract:

Integer multiply operations using data stored in an integer register file are performed using multi-media primitive instructions that operate on smaller operands. The present invention performs a multiply operation on a 32-bit or 64-bit value by performing multiply operations on a series of smaller operands to form partial products, and adding the partial products together. Data manipulation instructions are used to reposition 16-bit segments of the 32-bit operands into positions that allow the multi-media parallel multiply instructions to compute partial products, and the partial products are then added together to form the result. In every embodiment, the present invention achieves better latencies than the prior art method of performing integer multiply operations provided by the IA-64 architecture.

US Patent:

6986131, Jan 10, 2006

Filed:

Jun 18, 2002

Appl. No.:

10/175375

Inventors:

Carol L. Thompson - San Jose CA, US
Uma Srinivasan - Sunnyvale CA, US
Richard E. Hank - San Jose CA, US
Dale Morris - Steamboat Springs CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 9/45

US Classification:

717160, 717150, 712241, 712233

Abstract:

A method of efficient code generation for modulo scheduled uncounted loops includes: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to each instruction in each speculative stage; and using the stage predicate to conditionally enable or disable the execution of an instruction during the prologue and epilogue execution.