Dale C Potter

US Patent:

6414521, Jul 2, 2002

Filed:

Feb 1, 2001

Appl. No.:

09/775489

Inventors:

Dale A. Potter - Beaverton OR
Ravindar M. Lall - Portland OR

Assignee:

Lattice Semiconductor Corp. - Hillsboro OR

International Classification:

H03K 522

US Classification:

327 67, 327 51

Abstract:

A sense amplifier is provided that mitigates the effect of threshold voltage mismatch within the sense amplifier. The sense amplifier has an inverter pair coupled to the input terminals, with a resistive element coupled across output terminals of the inverter pair. Inverter gain stages following the inverter pair are coupled to a current limiting circuit to monitor and limit the current flowing through the inverter gain stage immediately following the inverter pair. The current limiting circuit allows the sense amplifier to be biased such that speed is improved while limiting power dissipation to acceptable levels, even under undesirable process, temperature, and power supply variations.

US Patent:

6462602, Oct 8, 2002

Filed:

Feb 1, 2001

Appl. No.:

09/775488

Inventors:

Dale A. Potter - Beaverton OR

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03L 500

US Classification:

327333, 327112, 327390

Abstract:

A voltage level translator is provided that operates over a wide range of voltage levels at a fast translation speed. The voltage level translator includes an input terminal that receives an input signal and a capacitor having its first terminal coupled to the input terminal. A clamp circuit is coupled to the input terminal and to the second terminal of the capacitor and operable to provide a signal on the second terminal of the capacitor in response to a first voltage level of the input signal. A voltage source circuit is coupled to the clamp circuit and to the second terminal of the capacitor and provides a signal on the second terminal of the capacitor in response to a second voltage level of the input signal. An output buffer has a first input terminal coupled to the first terminal of the capacitor and a second input terminal coupled to the second terminal of the capacitor. The output buffer provides an output signal having a translated voltage level on its output terminal in response to signals on the first and second terminals of the capacitor.

US Patent:

6639431, Oct 28, 2003

Filed:

Mar 29, 2002

Appl. No.:

10/112370

Inventors:

Dale A. Potter - Beaverton OR

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 522

US Classification:

327 65, 330253

Abstract:

A comparator circuit is disclosed that senses a differential input polarity even when operating with a common mode voltage near the power rails (e. g. , 50 millivolts) and under a wide range of process, temperature, and power supply conditions. In one aspect, the comparator circuit uses a complementary pair of P-type and N-type differential amplifiers. A combined P-type and N-type differential amplifier provides good transconductance even with a common mode voltage near either voltage rail. Consequently, a larger current swing than prior art circuits is provided to a current-to-voltage converter, which results in an overall faster circuit. In another aspect, a bias circuit drives a source follower that biases transistors in the differential amplifiers to ensure high transconductance and, consequently, high gain. Thus, the disclosed comparator senses differential input polarity even with a common mode voltage of only 50 millivolts or less.

US Patent:

60878541, Jul 11, 2000

Filed:

Sep 2, 1998

Appl. No.:

9/145793

Inventors:

Dale A. Potter - Beaverton OR

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 190185
H03K 190948

US Classification:

326 83

Abstract:

An improved line driver is disclosed. In one embodiment, the line driver has three inverters and a pass gate. The first inverter has a first input terminal connected directly to the input line of the line driver. The first inverter also has an output terminal coupled to a first output line of the line driver. The second inverter has an output node coupled to a second output line of the line driver. The third inverter has a first input terminal connected directly to the input line of the line driver and an output terminal coupled to the input node of the second inverter. The pass gate has a second input terminal coupled to the input line of the line driver and an output terminal coupled to both the second input terminal of the first inverter and the second input terminal of the third inverter. The pass gate receives an enable signal at a first input terminal and provides a conduction path between the input line of the line driver and the output terminal of the pass gate in response to the enable signal. The first and third inverters each invert the input signal to generate an output signal when the pass gate passes the input signal through.

US Patent:

62659006, Jul 24, 2001

Filed:

Apr 7, 1999

Appl. No.:

9/288062

Inventors:

Dale A. Potter - Beaverton OR

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19094
H03K 1920

US Classification:

326121

Abstract:

A CMOS OR circuit is fast and has a reduced sensitivity to the variations in the process, temperature and voltage supply. When the input signal to any one of a plurality of select transistor is in a logic high, a fixed supply of current is provided to the common drain terminal of the select transistors thereby to limit the amount of voltage swing of the common drain terminal and the common source terminal of the select transistors. A maximum power sensor senses the voltage differential developed between the common drain and the common source terminals of the select transistors and in response thereto generates a control signal which varies the amount of current that a variable current supply delivers to the common drain terminal thereby to prevent the output signal of the OR circuit from switching to the wrong state.