Dan Mihai Mocuta

US Patent:

6762469, Jul 13, 2004

Filed:

Apr 19, 2002

Appl. No.:

10/127196

Inventors:

Anda C. Mocuta - LaGrangeville NY
Meikei Ieong - Wappingers Falls NY
Ricky S. Amos - Rhinebeck NY
Diane C. Boyd - LaGrangeville NY
Dan M. Mocuta - LaGrangeville NY
Huajie Chen - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257407, 257391, 257392, 257376, 257402, 257204, 257 69, 257327, 257332, 438217, 438300, 438197, 438301, 438303

Abstract:

High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (Ë500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

US Patent:

6916698, Jul 12, 2005

Filed:

Mar 8, 2004

Appl. No.:

10/795672

Inventors:

Anda C. Mocuta - LaGrangeville NY, US
Meikei Ieong - Wappingers Falls NY, US
Ricky S. Amos - Rhinebeck NY, US
Diane C. Boyd - LaGrangeville NY, US
Dan M. Mocuta - LaGrangeville NY, US
Huajie Chen - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/8238

US Classification:

438217, 438223, 438224

Abstract:

High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

US Patent:

6958286, Oct 25, 2005

Filed:

Jan 2, 2004

Appl. No.:

10/751208

Inventors:

Huajie Chen - Danbury CT, US
Dan M. Mocuta - Lagrangeville NY, US
Richard J. Murphy - Clinton Corners NY, US
Stephan W. Bedell - Wappingers Falls NY, US
Devendra K. Sadana - Pleasantville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/28
H01L021/3205

US Classification:

438602, 438604, 438607, 438752, 438753, 438933

Abstract:

The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×10−1×10/cmof oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process which heats the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface sufficiently to remove additional oxygen from the surface and leave a second amount of oxygen, less than the first amount, on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The heating process leaves an amount of at least 5×10/cmof oxygen (typically, between approximately 1×10/cmand approximately 5×10/cmof oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface.

US Patent:

7071103, Jul 4, 2006

Filed:

Jul 30, 2004

Appl. No.:

10/710737

Inventors:

Kevin K. Chan - Staten Island NY, US
Huajie Chen - Danbury CT, US
Michael A. Gribelyuk - Stamford CT, US
Judson R. Holt - Wappingers Falls NY, US
Woo-Hyeong Lee - Poughquag NY, US
Ryan M. Mitchell - Wake Forest NC, US
Renee T. Mo - White Plains NY, US
Dan M. Mocuta - Lagrangeville NY, US
Werner A. Rausch - Stormville NY, US
Paul A. Ronsheim - Hopewell Junction NY, US
Henry K. Utomo - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438653, 438627, 438643

Abstract:

The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.

US Patent:

7202132, Apr 10, 2007

Filed:

Jan 16, 2004

Appl. No.:

10/707840

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Bruce B. Doris - Brewster NY, US
Dan M. Mocuta - Lagrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336

US Classification:

438300, 257377, 257E21619, 257E21622, 438299, 438311

Abstract:

Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.

US Patent:

7498602, Mar 3, 2009

Filed:

Apr 6, 2006

Appl. No.:

11/278910

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Bruce B. Doris - Brewster NY, US
Dan M. Mocuta - Lagrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336
H01L 21/84

US Classification:

257 19, 257288, 257330, 257E21619, 257E29193, 438151, 438299, 438300

Abstract:

Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.

US Patent:

7528027, May 5, 2009

Filed:

Mar 25, 2008

Appl. No.:

12/054727

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Mahender Kumar - Fishkill NY, US
Dan M. Mocuta - LaGrangeville NY, US
Ravikumar Ramachandran - Pleasantville NY, US
Wenjuan Zhu - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336

US Classification:

438197, 438149, 438151, 438158, 438199, 438264, 438268, 257209, 257255, 257347, 257365, 257E21249

Abstract:

An SOI CMOS structure includes a v-shape trench in a pFet region. The v-shape trench has a surface in a (111) plane and extends into an SOI layer in the pFet region. A layer, such as a gate oxide or high-k material, is formed in the v-shape trench. Poly-Si is deposited on top of the layer.

US Patent:

7550370, Jun 23, 2009

Filed:

Jan 16, 2004

Appl. No.:

10/597066

Inventors:

Huajie Chen - Danbury CT, US
Stephen W. Bedell - Wappingers Falls NY, US
Devendra K. Sadana - Pleasantville NY, US
Dan M. Mocuta - LaGrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438493, 438494, 438455

Abstract:

A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550 C. -700 C. ) HIPOX or steam oxidation, in-situ HCl etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCl, DCS and GeH.