Daniel J Baker

US Patent:

7434124, Oct 7, 2008

Filed:

Mar 28, 2006

Appl. No.:

11/391009

Inventors:

Daniel J. Baker - Austin TX, US
J. Christopher White - Austin TX, US
Ciro T. Nishiguchi - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G01R 31/28

US Classification:

714724, 714 30

Abstract:

A test system and method of configuring therefor. A test system includes a plurality of interface circuits for communicating with a device under test (DUT). The test system further includes a first memory for storing test vectors, a second memory for storing selection codes, and a third memory for storing configuration sets. Each selection code indicates an association between a test vector and a configuration set. Each configuration set may be associated with one or more of the test vectors. The configuration sets include information for configuring the interface circuits during communications between the test system and the DUT for each test vector. Each configuration set in the third memory is unique with respect to the other configuration sets, and the number of configuration sets may be less than the number of test vectors.

US Patent:

7478256, Jan 13, 2009

Filed:

Jan 24, 2006

Appl. No.:

11/338923

Inventors:

Craig M. Conway - Austin TX, US
Jeff A. Bergeron - Austin TX, US
Daniel J. Baker - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 1/12

US Classification:

713401, 713501, 326 93, 327141, 327162

Abstract:

System and method for synchronizing multiple devices coupled to a system timing module (STM) via respective first transmission media, wherein two or more of the respective first transmission media have different respective transmission times. The STM and devices share a common clock, in phase and with respect to a common reference. Each device is configured to transmit respective signals to the STM within a common clock cycle. Respective delays corresponding to the devices are determined based on the respective transmission times, where the respective delays are applicable to respective signals received from the devices to synchronize received corresponding pulses in the signals to within a common clock cycle. The respective delays are applied to respective signals received from the plurality of devices to synchronize received corresponding pulses in the signals to within the common clock cycle, after which the STM is operable to trigger the devices as a single device.

US Patent:

8638893, Jan 28, 2014

Filed:

Feb 24, 2012

Appl. No.:

13/404851

Inventors:

Stephen L. Dark - Austin TX, US
Daniel J. Baker - West Lafayette IN, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

H04B 1/10
H04L 25/49

US Classification:

375350, 375296

Abstract:

Various embodiments of communication devices and associated methods for reducing I/Q impairments in signals used by the communication devices are described. A transmitter device may perform filtering (or matrix multiplication) on digital I and Q signals to pre-correct them before converting them into analog I and Q signals. The pre-correction may pre-compensate for I/Q impairments which have not been introduced yet, but which will subsequently be introduced during digital to analog conversion, I/Q modulation, or other processing that occurs to produce a transmission signal from the original digital I and Q signals. A receiver device may receive a transmission signal, produce digital I and Q signals from it, and perform filtering on the digital I and Q signals to correct I/Q impairments at a plurality of frequency offsets.

US Patent:

20050046458, Mar 3, 2005

Filed:

Aug 28, 2003

Appl. No.:

10/651124

Inventors:

Charles Schroeder - Round Rock TX, US
Daniel Baker - Austin TX, US
Glen Sescila - Pflugerville TX, US

International Classification:

H03H011/26

US Classification:

327276000

Abstract:

A delay circuit. In one embodiment, a programmable logic device (PLD) is used to implement one or more delay circuits having a plurality of delay elements. Included in the plurality of elements are a balanced number of logic elements such that rising and falling edges of a signal passing through the delay circuit propagate with substantially the same amount of delay. The delay circuit may also include a selector circuit coupled to select an output from one of the plurality of delay elements. The delay circuit may be implemented such that it preserves the duty cycle and/or pulse width of signals to which the delay is applied.

US Patent:

20130218509, Aug 22, 2013

Filed:

Feb 16, 2012

Appl. No.:

13/398529

Inventors:

Charles G. Schroeder - Cedar Park TX, US
Christopher F. Graf - Liberty Hill TX, US
Ciro T. Nishiguchi - Austin TX, US
Nigel G. D'Souza - Austin TX, US
Daniel J. Baker - West Lafayette IN, US
Thomas D. Magruder - Austin TX, US

International Classification:

G06F 19/00

US Classification:

702123, 702108

Abstract:

Customizing a test instrument. A plurality of pairs of code modules may be provided. Each pair of code modules may include a first code module having program instructions for execution by a processor of the test instrument and a second code module for implementation on a programmable hardware element of the test instrument. For each pair of code modules, the first code module and the second code module may collectively implement a function in the test instrument. User input may be received specifying modification of a second code module of at least one of the plurality of pairs of code modules. Accordingly, a hardware description may be generated for the programmable hardware element of the test instrument based on the modified second code module.

US Patent:

20130219219, Aug 22, 2013

Filed:

Feb 16, 2012

Appl. No.:

13/398580

Inventors:

Charles G. Schroeder - Cedar Park TX, US
Christopher F. Graf - Liberty Hill TX, US
Ciro T. Nishiguchi - Austin TX, US
Nigel G. D'Souza - Austin TX, US
Daniel J. Baker - West Lafayette IN, US
Thomas D. Magruder - Austin TX, US

International Classification:

G06F 11/28

US Classification:

714 32, 714E11178

Abstract:

Customizing a test instrument. A plurality of pairs of code modules may be provided. Each pair of code modules may include a first code module having program instructions for execution by a processor of the test instrument and a second code module for implementation on a programmable hardware element of the test instrument. For each pair of code modules, the first code module and the second code module may collectively implement a function in the test instrument. User input may be received specifying modification of a second code module of at least one of the plurality of pairs of code modules. Accordingly, a hardware description may be generated for the programmable hardware element of the test instrument based on the modified second code module.

US Patent:

20130221871, Aug 29, 2013

Filed:

Feb 22, 2013

Appl. No.:

13/774914

Inventors:

CIRRUS LOGIC, INC. - , US
John L. Melanson - Austin TX, US
Daniel J. Baker - Austin TX, US

Assignee:

CIRRUS LOGIC, INC. - Austin TX

International Classification:

H05B 37/02

US Classification:

315254

Abstract:

In at least one embodiment, a system and method provide current compensation in a lighting system by controlling a lamp current to prevent a current through a triac-based dimmer from undershooting a holding current value. In at least one embodiment, at least one of the lamps includes a controller that controls circuitry in the lamp to draw more lamp current for a period of time than needed to illuminate a brightness of the lamp at a level corresponding to particular phase-cut angle of the supply voltage. By drawing more current than needed, the controller increases the dimmer current during the period of time to prevent the dimmer current from falling below the holding current value. In at least one embodiment, the period of time corresponds to a compensating pulse of the lamp current at a time when the dimmer current would otherwise fall below the holding current value.

US Patent:

RE331198, Nov 28, 1989

Filed:

Mar 7, 1988

Appl. No.:

7/168525

Inventors:

Daniel A. Baker - Minnetonka MN

Assignee:

Whirlpool Corporation - Benton Harbor MI

International Classification:

G01K 300
G01K 724
G06F 1520

US Classification:

374102

Abstract:

A method and apparatus is disclosed for determining the temperature to which a thermistor is exposed. A capacitor is charged through a reference resistor and the length of time required to charge the capacitor to a predetermined level is measured to obtain a reference charge time. The capacitor is discharged, and then charged through the thermistor and the length of time required to charge the capacitor to the predetermined level through the thermistor is measured to obtain a temperature charge time. The temperature to which the thermistor is exposed is determined by computing the difference between the reference charge time and the temperature charge time divided by the sum of the times.