Daniel J Blomberg

US Patent:

7972913, Jul 5, 2011

Filed:

May 28, 2009

Appl. No.:

12/474038

Inventors:

Xin Lin - Phoenix AZ, US
Daniel J. Blomberg - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/338

US Classification:

438167, 438169, 438534, 438570, 257E29317, 257E2145

Abstract:

Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.

US Patent:

8134219, Mar 13, 2012

Filed:

Jun 1, 2011

Appl. No.:

13/150831

Inventors:

Xin Lin - Phoenix AZ, US
Daniel J. Blomberg - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 27/095
H01L 29/47
H01L 29/812
H01L 31/07
H01L 31/108

US Classification:

257471, 257472, 257476, 257E29338

Abstract:

Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.

US Patent:

8198703, Jun 12, 2012

Filed:

Jan 18, 2010

Appl. No.:

12/689120

Inventors:

Xin Lin - Phoenix AZ, US
Daniel J. Blomberg - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/06

US Classification:

257603, 257106, 257175, 257199, 257481, 257E29335

Abstract:

A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region.

US Patent:

8212292, Jul 3, 2012

Filed:

Nov 20, 2009

Appl. No.:

12/622625

Inventors:

Xin Lin - Phoenix AZ, US
Daniel J. Blomberg - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 31/0328

US Classification:

257197, 257163, 257565, 257577, 257578, 257579, 257591, 257E27015

Abstract:

An improved bipolar transistor (′) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (′) comprises an emitter () having first () and second () portions of different depths (), a base () underlying the emitter () having a central portion () of a first base width () underlying the first portion () of the emitter (), a peripheral portion () having a second base width () larger than the first base width () partly underlying the second portion () of the emitter (), and a transition zone () of a third base width () and lateral extent () lying laterally between the first () and second () portions of the base (), and a collector () underlying the base (). The gain of the transistor (′) is much larger than a conventional bipolar transistor () made using the same CMOS process. By adjusting the lateral extent () of the transition zone (), the properties of the improved transistor (′) can be tailored to suit different applications without modifying the underlying CMOS IC process.

US Patent:

8384193, Feb 26, 2013

Filed:

Jan 26, 2011

Appl. No.:

13/014029

Inventors:

Xin Lin - Phoenix AZ, US
Daniel J. Blomberg - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/70

US Classification:

257579, 257197, 257565, 257587, 257591, 257E2903, 257E29114

Abstract:

Insufficient gain in bipolar transistors () is improved by providing an alloyed (e. g. , silicided) emitter contact () smaller than the overall emitter () area. The improved emitter () has a first emitter (FE) portion (-) of a first dopant concentration C, and a second emitter (SE) portion (-) of a second dopant concentration C. Preferably C≧C. The SE portion (-) desirably comprises multiple sub-regions () mixed with multiple sub-regions () of the FE portion (-). A semiconductor-metal alloy or compound (e. g. , a silicide) is desirably used for Ohmic contact () to the SE portion (-) but substantially not to the FE portion (-). Including the FE portion (-) electrically coupled to the SE portion (-) but not substantially contacting the emitter contact () on the SE portion (-) provides gain increases of as much as 278.

US Patent:

8546229, Oct 1, 2013

Filed:

Feb 6, 2013

Appl. No.:

13/760882

Inventors:

Xin Lin - Phoenix AZ, US
Daniel J. Blomberg - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/331
H01L 29/70

US Classification:

438338, 438309, 438316, 438335, 438342, 257E2903, 257E29114

Abstract:

Insufficient gain in bipolar transistors () is improved by providing an alloyed (e. g. , silicided) emitter contact () smaller than the overall emitter () area. The improved emitter () has a first emitter (FE) portion (-) of a first dopant concentration C, and a second emitter (SE) portion (-) of a second dopant concentration C. Preferably C≧C. The SE portion (-) desirably comprises multiple sub-regions () mixed with multiple sub-regions () of the FE portion (-). A semiconductor-metal alloy or compound (e. g. , a silicide) is desirably used for Ohmic contact () to the SE portion (-) but substantially not to the FE portion (-). Including the FE portion (-) electrically coupled to the SE portion (-) but not substantially contacting the emitter contact () on the SE portion (-) provides gain increases of as much as 278.

US Patent:

8648443, Feb 11, 2014

Filed:

Oct 20, 2010

Appl. No.:

12/908586

Inventors:

Xin Lin - Phoenix AZ, US
Daniel J. Blomberg - Chandler AZ, US
Hongning Yang - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/66

US Classification:

257565, 257E21608

Abstract:

Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.

US Patent:

20100187577, Jul 29, 2010

Filed:

Jan 26, 2009

Appl. No.:

12/359845

Inventors:

Xin Lin - Phoenix AZ, US
Daniel J. Blomberg - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

H01L 29/78
H01L 21/34

US Classification:

257280, 438167, 257E29271, 257E2146

Abstract:

Improved Schottky diodes () with reduced leakage current and improved breakdown voltage are provided by building a JFET () into the diode, serially located in the anode-cathode current path (). The gates of the JFET () formed by doped regions () placed above and below the diode's current path () are coupled to the anode () of the diode (), and the current path () passes through the channel region () of the JFET (). Operation is automatic so that as the reverse voltage increases, the JFET () channel region () pinches off, thereby limiting the leakage current and clamping the voltage across the Schottky junction () at a level below the Schottky junction () breakdown. Increased reverse voltage can be safely applied until the device eventually breaks down elsewhere. The impact on device area and area efficiency is minimal and the device can be built using a standard fabrication process so that it can be easily integrated into complex ICs.