Daniel E Dever

US Patent:

20030080782, May 1, 2003

Filed:

Oct 31, 2001

Appl. No.:

10/000258

Inventors:

Daniel Bailey - Northboro MA, US
Daniel Dever - Spencer MA, US
Ronald Preston - Malborough MA, US

International Classification:

H03K019/00

US Classification:

326/093000

Abstract:

A clock driver is disclosed that minimizes propagation delay, and thus improves the integrity of a clock distribution network. The clock driver preferably is implemented with silicon-on-insulator (SOI) technology, and comprises an inverter with an nFET and pFET that are body-connected. The body connection serves to reduce the body voltage of the pFET, while increasing the body voltage of the nFET. This shifting of the voltage reduces the voltage threshold differential for both the nFET and pFET, which translates into a design that experiences less propagation delay due to voltage variations and fluctuations. If desired, the body voltages may be slightly offset from each other by placing one or more voltage drop transistors in the conductive path between the bodies of the nFET and pFET. In addition, the present invention may be used to design a programmable inverter that can operate in a low power mode, or in a high precision mode.

US Patent:

20130111000, May 2, 2013

Filed:

Oct 31, 2011

Appl. No.:

13/285773

Inventors:

David Kravitz - Cambridge MA, US
Daniel E. Dever - North Brookfield MA, US

Assignee:

Cavium, Inc. - San Jose CA

International Classification:

G06F 15/173

US Classification:

709223

Abstract:

A network processor includes a schedule, sync and order (SSO) module for scheduling and assigning work to multiple processors. The SSO includes an on-deck unit (ODU) that provides a table having several entries, each entry storing a respective work queue entry, and a number of lists. Each of the lists may be associated with a respective processor configured to execute the work, and includes pointers to entries in the table. A pointer is added to the list based on an indication of whether the associated processor accepts the WQE corresponding to the pointer.

US Patent:

20210374057, Dec 2, 2021

Filed:

Aug 12, 2021

Appl. No.:

17/400959

Inventors:

- Singapore, SG
David ASHER - Sutton MA, US
Richard KESSLER - Northborough MA, US
Bradley DOBBIE - Medford MA, US
Daniel DEVER - North Brookfield MA, US
Thomas F. HUMMEL - Westborough MA, US
Isam AKKAWI - Santa Clara CA, US

International Classification:

G06F 12/084
G06F 12/0842
G06F 12/0813

Abstract:

Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.

US Patent:

20200250088, Aug 6, 2020

Filed:

Jan 31, 2019

Appl. No.:

16/264386

Inventors:

- Santa Clara CA, US
David Asher - Sutton MA, US
Richard Kessler - Northborough MA, US
Brad Dobbie - Medford MA, US
Daniel Dever - North Brookfield MA, US
Tom Hummel - Westborough MA, US
Isam Akkawi - Santa Clara CA, US

International Classification:

G06F 12/084
G06F 12/0842

Abstract:

Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.

US Patent:

20200097292, Mar 26, 2020

Filed:

Sep 25, 2018

Appl. No.:

16/140936

Inventors:

- Hamilton, BM
Shubhendu Sekhar MUKHERJEE - Southborough MA, US
Michael BERTONE - Marlborough MA, US
David Asher - Sutton MA, US
Daniel DEVER - North Brookfield MA, US
Bradley D. DOBBIE - Medford MA, US
Tom HUMMEL - Holliston MA, US

International Classification:

G06F 9/30
G06F 9/38
G06F 12/1045

Abstract:

Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction. The second high-level instruction occurs after the first high-level instruction within a series of high-level instructions, and delaying insertion of the low-level instruction provided for performing the operation into an insertion position within the series of low-level instructions, where the delaying causes the insertion position to be between a final low-level instruction converted from the first high-level instruction and an initial low-level instruction converted from the second high-level instruction.

US Patent:

20160140060, May 19, 2016

Filed:

Nov 14, 2014

Appl. No.:

14/541902

Inventors:

- San Jose CA, US
David Asher - Sutton MA, US
Brad Dobbie - Cambridge MA, US
Tom Hummel - Holliston MA, US
Daniel Dever - North Brookfield MA, US

International Classification:

G06F 13/16
G06F 12/10
G06F 13/40

Abstract:

A motherboard includes multiple sockets, each socket configured to accept an integrated circuit. A first integrated circuit in a first socket includes one or more cores and at least one buffer. A second integrated circuit in a second socket includes one or more cores and at least one buffer. Communication circuitry transfers messages to buffers of integrated circuits coupled to different sockets. A first core on the first integrated circuit is configured to send messages corresponding to multiple types of instructions to a second core on the second integrated circuit through the communication circuitry. The buffer of the second integrated circuit is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores on the first integrated circuit at the same time, and still have enough storage space for one or more instructions of a first type.

US Patent:

20160140061, May 19, 2016

Filed:

Nov 14, 2014

Appl. No.:

14/542118

Inventors:

- San Jose CA, US
David Asher - Sutton MA, US
Brad Dobbie - Cambridge MA, US
Tom Hummel - Holliston MA, US
Daniel Dever - North Brookfield MA, US

International Classification:

G06F 13/16
G06F 13/42
G06F 13/40
G06F 12/10

Abstract:

Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering messages in a second buffer associated with a second set of multiple cores; and transferring messages over communication circuitry from cores not in the first set to the first buffer, and to transferring messages from cores not in the second set to the second buffer. A first core of the first set sends messages corresponding to multiple types of instructions to a second core of the second set through the communication circuitry. The second buffer is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores in the first set at the same time, and still have enough storage space for one or more instructions of a first type.

US Patent:

20150220360, Aug 6, 2015

Filed:

Feb 3, 2014

Appl. No.:

14/171290

Inventors:

- San Jose CA, US
Richard Eugene Kessler - Northboroug MA, US
Daniel Edward Dever - North Brookfield MA, US
Nitin Dhiroobhai Godiwala - Boylston MA, US

Assignee:

CAVIUM, INC. - San Jose CA

International Classification:

G06F 9/48
G06F 9/50

Abstract:

A method and a system embodying the method for pre-fetching and processing work for processor cores in a network processor, comprising requesting pre-fetch work by a requestor; determining that the work may be pre-fetched for the requestor; searching for the work to pre-fetch; and pre-fetching the found work into one of one or more pre-fetch work-slots associated with the requestor is disclosed.