Daniel E Dever

US Patent:

20130111000, May 2, 2013

Filed:

Oct 31, 2011

Appl. No.:

13/285773

Inventors:

David Kravitz - Cambridge MA, US
Daniel E. Dever - North Brookfield MA, US

Assignee:

Cavium, Inc. - San Jose CA

International Classification:

G06F 15/173

US Classification:

709223

Abstract:

A network processor includes a schedule, sync and order (SSO) module for scheduling and assigning work to multiple processors. The SSO includes an on-deck unit (ODU) that provides a table having several entries, each entry storing a respective work queue entry, and a number of lists. Each of the lists may be associated with a respective processor configured to execute the work, and includes pointers to entries in the table. A pointer is added to the list based on an indication of whether the associated processor accepts the WQE corresponding to the pointer.

US Patent:

20200097292, Mar 26, 2020

Filed:

Sep 25, 2018

Appl. No.:

16/140936

Inventors:

- Hamilton, BM
Shubhendu Sekhar MUKHERJEE - Southborough MA, US
Michael BERTONE - Marlborough MA, US
David Asher - Sutton MA, US
Daniel DEVER - North Brookfield MA, US
Bradley D. DOBBIE - Medford MA, US
Tom HUMMEL - Holliston MA, US

International Classification:

G06F 9/30
G06F 9/38
G06F 12/1045

Abstract:

Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction. The second high-level instruction occurs after the first high-level instruction within a series of high-level instructions, and delaying insertion of the low-level instruction provided for performing the operation into an insertion position within the series of low-level instructions, where the delaying causes the insertion position to be between a final low-level instruction converted from the first high-level instruction and an initial low-level instruction converted from the second high-level instruction.