Daniel L Jaeger

US Patent:

20210141610, May 13, 2021

Filed:

Nov 8, 2019

Appl. No.:

16/677717

Inventors:

- Santa Clara CA, US
Julien Frougier - Albany NY, US
Ryan W. Sporer - Mechanicville NY, US
George R. Mulfinger - Wilton NY, US
Daniel Jaeger - Saratoga Springs NY, US

Assignee:

GLOBALFOUNDRIES U.S. Inc. - Santa Clara CA

International Classification:

G06F 7/58
H04L 9/32
H01L 29/772
H01L 27/07
H01L 21/8234

Abstract:

Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

US Patent:

20200411689, Dec 31, 2020

Filed:

Jun 30, 2019

Appl. No.:

16/458178

Inventors:

- GRAND CAYMAN, KY
DANIEL JAEGER - Saratoga Springs NY, US
MAN GU - Malta NY, US
BRADLEY MORGENFELD - Greenfield Center NY, US
HAITING WANG - Clifton Park NY, US
KAVYA SREE DUGGIMPUDI - Clifton Park NY, US
WANG ZHENG - Ballston Lake NY, US

International Classification:

H01L 29/78
H01L 29/66
H01L 21/822

Abstract:

A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.

US Patent:

20200335591, Oct 22, 2020

Filed:

Apr 17, 2019

Appl. No.:

16/386363

Inventors:

- Grand Cayman, KY
Daniel Jaeger - Saratoga Springs NY, US
Naved Siddiqui - Malta NY, US
Jessica Dechene - Watervliet NY, US
Daniel J. Dechene - Watervliet NY, US
Shreesh Narasimha - Charlotte NC, US

International Classification:

H01L 29/417
H01L 27/088
H01L 21/311
H01L 21/033
H01L 29/40

Abstract:

Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

US Patent:

20200203480, Jun 25, 2020

Filed:

Dec 24, 2018

Appl. No.:

16/231671

Inventors:

- Grand Cayman, KY
Veeraraghavan S. BASKER - Schenectady NY, US
Brian J. GREENE - Wappingers Falls NY, US
Kai ZHAO - Hopewell Junction NY, US
Daniel JAEGER - Saratoga Springs NY, US
Keith TABAKMAN - Wilton NY, US
Christopher NASSAR - Malta NY, US

Assignee:

GLOBALFOUNDRIES INC. - GRAND CAYMAN

International Classification:

H01L 29/06
H01L 29/417
H01L 29/66
H01L 29/78
H01L 21/8234

Abstract:

A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.

US Patent:

20200013672, Jan 9, 2020

Filed:

Sep 17, 2019

Appl. No.:

16/573209

Inventors:

- GRAND CAYMAN, KY
Daniel JAEGER - Saratoga Springs NY, US
Chih-Chiang CHANG - Clifton Park NY, US
Michael AQUILINO - Gansevoort NY, US
Patrick CARPENTER - Hanover MD, US
Junsic HONG - Malta NY, US
Mitchell RUTKOWSKI - Ballston Spa NY, US
Huy CAO - Rexford NY, US

International Classification:

H01L 21/768
H01L 21/28
H01L 29/66
H01L 21/311

Abstract:

The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

US Patent:

20190393077, Dec 26, 2019

Filed:

Jun 25, 2018

Appl. No.:

16/016910

Inventors:

- Grand Cayman, KY
Jiehui Shu - Clifton Park NY, US
Pei Liu - Rexford NY, US
Jinping Liu - Ballston Lake NY, US
Haiting Wang - Clifton Park NY, US
Daniel J. Jaeger - Saratoga Springs NY, US

International Classification:

H01L 21/762
H01L 29/66
H01L 21/768
H01L 29/78
H01L 21/8234
H01L 27/088

Abstract:

The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

US Patent:

20190326408, Oct 24, 2019

Filed:

Jun 29, 2019

Appl. No.:

16/458056

Inventors:

- GRAND CAYMAN, KY
Daniel Jaeger - Saratoga Springs NY, US
Veeraraghavan Basker - Albany NY, US
Christopher Nassar - Ballston Spa NY, US
Jinsheng Gao - Clifton Park NY, US
Michael Aquilino - Gansevoort NY, US

Assignee:

GLOBALFOUNDRIES INC. - GRAND CAYMAN

International Classification:

H01L 29/49
H01L 21/8234
H01L 29/78
H01L 29/66
H01L 21/02
H01L 21/8238
H01L 21/225
H01L 21/321
H01L 27/092
H01L 29/417
H01L 21/28

Abstract:

At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

US Patent:

20190295898, Sep 26, 2019

Filed:

May 6, 2019

Appl. No.:

16/403745

Inventors:

- Grand Cayman, KY
Daniel Jaeger - Saratoga Springs NY, US
Chanro Park - Clifton Park NY, US
Laertis Economikos - Wappingers Falls NY, US
Haiting Wang - Clifton Park NY, US
Hui Zang - Guilderland NY, US

International Classification:

H01L 21/8234
H01L 21/762
H01L 27/088
H01L 29/66
H01L 21/311

Abstract:

Structures and methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. A sacrificial layer may be disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. Alternatively, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.