Daniel F Johnston

US Patent:

7061501, Jun 13, 2006

Filed:

Nov 7, 2000

Appl. No.:

09/708230

Inventors:

Adam T. Lake - Beaverton OR, US
Marc S. Blackstein - Hillsboro OR, US
Carl S. Marshall - Portland OR, US
Daniel Johnston - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 5/00

US Classification:

345582, 345583, 345585, 345586, 345588, 345440, 345426, 345473

Abstract:

A pencil-sketch image is rendered from three-dimensional (3D) data by determining a pencil-sketch texture for a polygon defined by the 3D data, projecting the polygon onto a two-dimensional surface, and mapping the pencil-sketch texture onto the polygon to render the pencil-sketch image. The pencil-sketch texture is determined by obtaining a value based on a normal vector to the polygon and a light vector between the polygon and a light source, classifying the polygon based on the value, and associating the pencil-sketch texture with the polygon based on the classification of the polygon.

US Patent:

7274372, Sep 25, 2007

Filed:

Nov 6, 2000

Appl. No.:

09/707344

Inventors:

Adam T. Lake - Portland OR, US
Carl S. Marshall - Portland OR, US
Marc S. Blackstein - Hillsboro OR, US
Daniel Johnston - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 5/00

US Classification:

345582

Abstract:

A real-time digital engraving technique gives the appearance of traditional copperplate engraving. The present system accepts a 3D mesh comprising vertex data and applies a novel algorithm to generate a digital engraving image based on the mesh. The present method works on any 3D model, generates the resulting image in real-time, allows the user to dynamically change views, and does not require user intervention.

US Patent:

20060101434, May 11, 2006

Filed:

Sep 30, 2004

Appl. No.:

10/955873

Inventors:

Adam Lake - Portland OR, US
Chris Wilkerson - Portland OR, US
Carl Marshall - Portland OR, US
Daniel Johnston - Portland OR, US

International Classification:

G06F 9/45

US Classification:

717140000

Abstract:

A method, apparatus, and system are provided for reducing register file bandwidth using bypass logic control. According to one embodiment, a source code is translated into an intermediate code, which is then to be translated into an executable code. A bypass control logic description file is accessed to perform a lookup of description information at the description file. The description information is then used to compile the intermediate code into the executable.

US Patent:

59969695, Dec 7, 1999

Filed:

Apr 17, 1998

Appl. No.:

9/062245

Inventors:

Daniel S. Johnston - Salem OR
Michael A. Quesada - Aumsville OR

International Classification:

B25C 1100

US Classification:

254 28

Abstract:

A staple removal tool includes an elongated handle mounting a U-shaped cover member supporting a U-shaped base member formed with a forwardly projecting staple lifter tongue. A crimping arm is pivoted on the base member for movement toward and away from the staple lifter tongue and is actuated by a hand lever located under the handle and pivotally secured at its forward end to the cover member. A spring loaded link member is attached at one end to the hand lever and at the opposite end to the crimping arm, whereby pivoting of the handle lever effects pivotal movement of the crimping arm. A crimping bar is secured to and spaced from the base member to receive the clamping arm between them. The staple lifter tongue engages under the bridge portion of a staple, such as a roofing staple, and leveraging of the handle pulls the staple from its wood anchor. If the staple breaks, or if only one leg pulls out of the wood, the upwardly projecting length of staples still anchored in wood is placed alongside the confronting sides of the tongue and crimping bar and the hand lever manipulated to pivot the clamping arm into the space between the tongue and crimping bar, whereby to bend the staple leg to U-shape around the clamping arm and secure it against release, allowing the handle to leverage the resistant leg out of the wood.

US Patent:

20220366630, Nov 17, 2022

Filed:

Jul 28, 2022

Appl. No.:

17/876358

Inventors:

- Santa Clara CA, US
ZACK WATERS - Portland OR, US
MICHAEL APODACA - El Dorado Hills CA, US
DANIEL JOHNSTON - Portland OR, US
JASON SURPRISE - Beaverton OR, US
PRASOONKUMAR SURTI - Folsom CA, US
SUBRAMANIAM MAIYURAN - Gold River CA, US
PETER DOYLE - Gold River CA, US
SAURABH SHARMA - El Dorado Hills CA, US
ANKUR SHAH - Folsom CA, US
MURALI RAMADOSS - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 15/00
G06T 15/40
G06T 15/80

Abstract:

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

US Patent:

20210272349, Sep 2, 2021

Filed:

May 3, 2021

Appl. No.:

17/306769

Inventors:

- Santa Clara CA, US
ZACK WATERS - Portland OR, US
MICHAEL APODACA - Folsom CA, US
DANIEL JOHNSTON - Portland OR, US
JASON SURPRISE - Beaverton OR, US
PRASOONKUMAR SURTI - Folsom CA, US
SUBRAMANIAM MAIYURAN - Gold River CA, US
PETER DOYLE - El Dorado Hills CA, US
SAURABH SHARMA - El Dorado Hills CA, US
ANKUR SHAH - Folsom CA, US
MURALI RAMADOSS - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 15/00
G06T 15/40
G06T 15/80

Abstract:

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

US Patent:

20200074713, Mar 5, 2020

Filed:

Aug 29, 2018

Appl. No.:

16/116158

Inventors:

TRAVIS SCHLUESSLER - Berthoud CO, US
ZACK WATERS - Portland OR, US
MICHAEL APODACA - Folsom CA, US
DANIEL JOHNSTON - Portland OR, US
JASON SURPRISE - Beaverton OR, US
PRASOONKUMAR SURTI - Folsom CA, US
SUBRAMANIAM MAIYURAN - Gold River CA, US
PETER DOYLE - El Dorado Hills CA, US
SAURABH SHARMA - El Dorado Hills CA, US
ANKUR SHAH - Folsom CA, US
MURALI RAMADOSS - Folsom CA, US

International Classification:

G06T 15/00
G06T 15/80
G06T 15/40

Abstract:

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.