Daniel P Mccarthy

US Patent:

6766433, Jul 20, 2004

Filed:

Sep 21, 2001

Appl. No.:

09/957780

Inventors:

Joseph C. Circello - Phoenix AZ
Daniel M. McCarthy - Phoenix AZ
Henri Cloetens - Vilvoorde, BE
Nancy H. Woo - Austin TX
Bridget C. Hooser - Munich, DE

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 1210

US Classification:

711202, 711220, 714702

Abstract:

A system ( ) implements user programmable addressing modes in response to control information contained within an input address. Encoded control information stored in a plurality of user programmed address permutation control registers ( ) is used to determine what bit values are used to replace predetermined bits of the input address to selectively create a corresponding permutated address. Since no modification to a processors pipeline is required, various permutation addressing modes may be user-defined and implemented using either a general-purpose processor or a specialized processor.

US Patent:

7433803, Oct 7, 2008

Filed:

Apr 27, 2005

Appl. No.:

11/116672

Inventors:

Joseph C. Circello - Phoenix AZ, US
Daniel M. McCarthy - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 11/30

US Classification:

702186, 702182, 714 38, 714 37, 714 39, 714 47, 714E112, 717127, 712227

Abstract:

A system and method for performance monitoring in processors is provided. The system and method evaluates the performance of the processor by counting selected events during one or more defined periods. The performance monitor provides improved performance characterization by providing highly-configurable start-stop control over the event counting.

US Patent:

8312253, Nov 13, 2012

Filed:

Feb 22, 2008

Appl. No.:

12/035961

Inventors:

Joseph C. Circello - Phoenix AZ, US
Daniel M. McCarthy - Phoenix AZ, US
Sylvia M. Thirtle - Pittsford NY, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 9/00

US Classification:

712227

Abstract:

In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to allow the trace buffer information to be accessed at an external interface to the integrated circuit device. The CPU is continually halted as the trace buffer is filled to facilitate retrieving all information written to the trace buffer.

US Patent:

8417924, Apr 9, 2013

Filed:

Feb 22, 2008

Appl. No.:

12/035969

Inventors:

Joseph C. Circello - Phoenix AZ, US
Daniel M. McCarthy - Phoenix AZ, US
David J. Schimke - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 9/44

US Classification:

712244

Abstract:

A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.

US Patent:

20090217298, Aug 27, 2009

Filed:

Feb 22, 2008

Appl. No.:

12/035967

Inventors:

Joseph C. Circello - Phoenix AZ, US
Ujwala R. Malwade - Austin TX, US
Daniel M. McCarthy - Phoenix AZ, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

G06F 13/00

US Classification:

719318

Abstract:

A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.

US Patent:

20130326193, Dec 5, 2013

Filed:

May 31, 2012

Appl. No.:

13/485078

Inventors:

DANIEL M. MCCARTHY - Phoenix AZ, US
Joseph C. Circello - Phoenix AZ, US
Kristen A. Hausman - Austin TX, US

International Classification:

G06F 9/30

US Classification:

712207, 712E09016

Abstract:

Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.

US Patent:

57612153, Jun 2, 1998

Filed:

Jul 7, 1997

Appl. No.:

8/888384

Inventors:

Daniel M. McCarthy - Phoenix AZ
Paul W. Hollis - Austin TX
Ruey J. Yu - Austin TX
Renny L. Eisele - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1100

US Classification:

371 2231

Abstract:

Accurate delay testing of integrated circuits containing memory arrays embedded in combinational logic utilizes actual memory array timing. Actual memory timing signals provide the timing for bypassing the memory in SCAN Mode. The result is that simulated memory accesses during SCAN Mode testing have the same timing as actual memory accesses have during functional mode operation. Thus delay testing during SCAN Mode through paths containing both combinational logic and memory arrays accurately determines path delays.

US Patent:

54856027, Jan 16, 1996

Filed:

Dec 27, 1993

Appl. No.:

8/172985

Inventors:

William B. Ledbetter - Austin TX
Daniel M. McCarthy - Phoenix AZ
James G. Gay - Pflugerville TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 104

US Classification:

395550

Abstract:

A data processing system receives a CLK signal for performing operations internal to a data processor (10). The data processor (10) has a CPU (12) which performs operations in response to the CLK signal. The bus is allowed to operate at a frequency which is less than or equal to the operational frequency of the CLK. The bus clock is typically either equal to the clock in frequency or runs at one-half or one-quarter speed. A CLKEN* signal input to the processor (10) is asserted to indicate an active edge of the external bus clock and synchronize the active edge of the external bus clock with an active edge of CLK to allow an active edge of CLK to perform bus operations which coincide with the active edge of the external bus clock. In another form, an internal counter/control circuit (20) may be used internal to the processor (10) to generate internal CLKEN* signals.