Daniel D Morris

US Patent:

20230075959, Mar 9, 2023

Filed:

May 5, 2022

Appl. No.:

17/737820

Inventors:

- Menlo Park CA, US
Daniel Henry MORRIS - Mountain View CA, US
Edith DALLARD - San Mateo CA, US

International Classification:

G11C 7/10
G11C 7/12
G11C 8/18
G11C 8/08

Abstract:

An SRAM controller for performing sequential accesses using internal ports that operate concurrently on different rows. Each internal port includes a row address strobe (RAS) timer that generates clock signals controlling the timing of operations during a RAS phase in which word line decoding is performed once for a group of bit cells being accessed. The RAS phase can involve additional conditioning operations, such as precharging of local bits lines associated with the group of bit cells. The RAS phase is followed by an input/output (IO) phase in which individual bit cells are accessed in sequential address order using a column select signal generated by an IO timer. The RAS phase of a first internal port can be at least partially overlapped by the IO phase of a second internal port to hide the RAS latency of the first internal port. The IO timer can be shared among internal ports.

US Patent:

20230065165, Mar 2, 2023

Filed:

Dec 17, 2021

Appl. No.:

17/554838

Inventors:

- Menlo Park CA, US
Huichu LIU - Santa Clara CA, US
Daniel Henry MORRIS - Mountain View CA, US
Doyun KIM - Seoul, KR

International Classification:

G11C 11/419
G11C 11/418

Abstract:

In some embodiments, an apparatus comprises: a static random access memory (SRAM) device. The SRAM device may have a bit cell array comprising a plurality of bit cells, the plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column of the plurality of columns operatively coupled to a pair of bit lines. The apparatus may comprise a controller configured to: assert a word line associated with a row; perform a sequence of write operations while the word line remains asserted, each write operation corresponding to a bit cell associated with a different column of the plurality of columns and the row, wherein the word line has an elevated voltage relative to a non-elevated voltage during at least a portion of the sequence of write operations; and de-assert the word line after the sequence of write operations are performed.

US Patent:

20230065591, Mar 2, 2023

Filed:

Apr 11, 2022

Appl. No.:

17/658740

Inventors:

- Menlo Park CA, US
Edith DALLARD - San Mateo CA, US
Daniel Henry MORRIS - Mountain View CA, US

International Classification:

G11C 29/44
G11C 29/18
G11C 29/12
G11C 29/00
H03K 19/173
H03K 19/21

Abstract:

In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns. The SRAM device further comprises a plurality of column decoders, each associated with a column group of the plurality of column groups. In some embodiments, the controller may be configured to read the local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns.

US Patent:

20210089448, Mar 25, 2021

Filed:

Sep 19, 2019

Appl. No.:

16/576687

Inventors:

- Santa Clara CA, US
Tanay Karnik - Portland OR, US
Tejpal Singh - Shrewsbury MA, US
Yen-Cheng Liu - Portland OR, US
Lavanya Subramanian - Santa Clara CA, US
Mahesh Kumashikar - Bangalore, IN
Sreenivas Subramoney - Bangalore, IN
Kaushik Vaidyanathan - Santa Clara CA, US
Daniel H. Morris - Palo Alto CA, US
Uygar E. Avci - Portland OR, US
Ian A. Young - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/0804
G06F 11/20
G06F 12/0806
G06F 12/0866

Abstract:

Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

US Patent:

20200321446, Oct 8, 2020

Filed:

Sep 28, 2017

Appl. No.:

16/635739

Inventors:

- Santa Clara CA, US
Uygar E. AVCI - Portland OR, US
Joshua M. HOWARD - Portland OR, US
Ian A. YOUNG - Portland OR, US
Daniel H. MORRIS - Hillsboro OR, US

International Classification:

H01L 29/66
H01L 29/51

Abstract:

Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side

US Patent:

20200194663, Jun 18, 2020

Filed:

Dec 12, 2018

Appl. No.:

16/217807

Inventors:

Huichu Liu - Santa Clara CA, US
Daniel Morris - Hillsboro OR, US
Tanay Karnik - Portland OR, US
Sasikanth Manipatruni - Hillsboro OR, US
Kaushik Vaidyanathan - Santa Clara CA, US
Ian Young - Portland OR, US

International Classification:

H01L 43/02
H01L 43/10
H01L 27/22
H03K 19/18

Abstract:

Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.

US Patent:

20200105743, Apr 2, 2020

Filed:

Sep 28, 2018

Appl. No.:

16/147512

Inventors:

- Santa Clara CA, US
Daniel H. MORRIS - Hillsboro OR, US
Ian A. YOUNG - Portland OR, US

International Classification:

H01L 27/07
H01L 25/18
H01L 29/88
H01L 29/51
H01L 27/02

Abstract:

An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.

US Patent:

20200105774, Apr 2, 2020

Filed:

Sep 28, 2018

Appl. No.:

16/146938

Inventors:

- Santa Clara CA, US
Daniel H. Morris - Hillsboro OR, US
Uygar E. Avci - Portland OR, US
Ian A. Young - Portland OR, US

International Classification:

H01L 27/11514
H01L 27/11509
G11C 11/22
H01L 23/532
H01L 23/528
H01L 25/18

Abstract:

An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.