Daniel Robert Morris

US Patent:

45535612, Nov 19, 1985

Filed:

Jun 22, 1984

Appl. No.:

6/623476

Inventors:

Daniel C. Morris - Downers Grove IL

International Classification:

E03F 512
A47K 114

US Classification:

137362

Abstract:

A novel device for the control of flooding from drainage system overflow and a method of use are disclosed. The device is useful for limiting overflow from drainage structures, such as a sump well or sewer drain. The device includes at least one container segment that defines an enclosure for retaining excess flood water. The device also includes a cover and means for removably mounting the cover on the top of the container segment. Transition means are also provided to sealingly connect the container segment with an element below the container segment. In accordance with a method aspect of this invention, a flood control installation is made by attaching the device to an apron defining the opening about the well.

US Patent:

20210089448, Mar 25, 2021

Filed:

Sep 19, 2019

Appl. No.:

16/576687

Inventors:

- Santa Clara CA, US
Tanay Karnik - Portland OR, US
Tejpal Singh - Shrewsbury MA, US
Yen-Cheng Liu - Portland OR, US
Lavanya Subramanian - Santa Clara CA, US
Mahesh Kumashikar - Bangalore, IN
Sreenivas Subramoney - Bangalore, IN
Kaushik Vaidyanathan - Santa Clara CA, US
Daniel H. Morris - Palo Alto CA, US
Uygar E. Avci - Portland OR, US
Ian A. Young - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/0804
G06F 11/20
G06F 12/0806
G06F 12/0866

Abstract:

Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

US Patent:

20200321446, Oct 8, 2020

Filed:

Sep 28, 2017

Appl. No.:

16/635739

Inventors:

- Santa Clara CA, US
Uygar E. AVCI - Portland OR, US
Joshua M. HOWARD - Portland OR, US
Ian A. YOUNG - Portland OR, US
Daniel H. MORRIS - Hillsboro OR, US

International Classification:

H01L 29/66
H01L 29/51

Abstract:

Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side

US Patent:

20200194663, Jun 18, 2020

Filed:

Dec 12, 2018

Appl. No.:

16/217807

Inventors:

Huichu Liu - Santa Clara CA, US
Daniel Morris - Hillsboro OR, US
Tanay Karnik - Portland OR, US
Sasikanth Manipatruni - Hillsboro OR, US
Kaushik Vaidyanathan - Santa Clara CA, US
Ian Young - Portland OR, US

International Classification:

H01L 43/02
H01L 43/10
H01L 27/22
H03K 19/18

Abstract:

Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.

US Patent:

20200105743, Apr 2, 2020

Filed:

Sep 28, 2018

Appl. No.:

16/147512

Inventors:

- Santa Clara CA, US
Daniel H. MORRIS - Hillsboro OR, US
Ian A. YOUNG - Portland OR, US

International Classification:

H01L 27/07
H01L 25/18
H01L 29/88
H01L 29/51
H01L 27/02

Abstract:

An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.

US Patent:

20200105774, Apr 2, 2020

Filed:

Sep 28, 2018

Appl. No.:

16/146938

Inventors:

- Santa Clara CA, US
Daniel H. Morris - Hillsboro OR, US
Uygar E. Avci - Portland OR, US
Ian A. Young - Portland OR, US

International Classification:

H01L 27/11514
H01L 27/11509
G11C 11/22
H01L 23/532
H01L 23/528
H01L 25/18

Abstract:

An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.

US Patent:

20200098415, Mar 26, 2020

Filed:

Jul 23, 2018

Appl. No.:

16/615780

Inventors:

- Santa Clara CA, US
Sasikanth Manipatruni - Portland OR, US
Ian A. Young - Portland OR, US
Tanay Karnik - Portland OR, US
Daniel H. Morris - San Francisco CA, US
Kaushik Vaidyanathan - Santa Clara CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 11/22
H01L 27/11507
H01L 49/02

Abstract:

Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line; a second multiplexer coupled to the source-line; a first driver coupled to the first multiplexer; a second driver coupled to the second multiplexer; and a current source coupled to the first and second drivers.

US Patent:

20200091407, Mar 19, 2020

Filed:

Sep 13, 2018

Appl. No.:

16/130905

Inventors:

Huichu LIU - Santa Clara CA, US
Tanay KARNIK - Portland OR, US
Sasikanth MANIPATRUNI - Portland OR, US
Daniel MORRIS - Hillsboro OR, US
Kaushik VAIDYANATHAN - Santa Clara CA, US
Ian YOUNG - Portland OR, US

International Classification:

H01L 43/02
H01L 43/10
G11C 11/16
G11C 11/18
H01L 43/06

Abstract:

An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.