Daniel J Woo

US Patent:

8604852, Dec 10, 2013

Filed:

Sep 11, 2012

Appl. No.:

13/610469

Inventors:

Sebastian Turullols - Los Altos CA, US
Changku Hwang - Morgan Hill CA, US
Daniel Woo - San Francisco CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

H03L 7/06

US Classification:

327159, 327298, 327262

Abstract:

In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency that is less than the first fundamental frequency. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage so that an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced. For example, the control logic may select the first DCO if the instantaneous value of the power-supply voltage is greater than the average power-supply voltage; otherwise, the control logic may select the second DCO.

US Patent:

20150365093, Dec 17, 2015

Filed:

Sep 26, 2014

Appl. No.:

14/498744

Inventors:

- Redwood City CA, US
Sebastian Turullols - Los Altos CA, US
Changku Hwang - Morgan Hill CA, US
Daniel S. Woo - San Francisco CA, US

International Classification:

H03L 7/08
H03L 7/099

Abstract:

In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.