Daniel C Wu

US Patent:

6829739, Dec 7, 2004

Filed:

Aug 10, 2000

Appl. No.:

09/636209

Inventors:

Daniel Wu - Mountain View CA

Assignee:

Siemens Information and Communication Networks, Inc. - Boca Raton FL

International Classification:

G11C 2900

US Classification:

714719

Abstract:

Memory segment overwrites are detected by providing a redundant header at the end of a segment and comparing a redundant header to an initial header. In specific embodiments, overwrites may be detected both after segment writes and prior to buffer reads. In further embodiments, some header overwrite errors may be corrected to increase the mean time between failure of a logic system.

US Patent:

20210240634, Aug 5, 2021

Filed:

Apr 22, 2021

Appl. No.:

17/237391

Inventors:

- Dallas TX, US
Joseph Zbiciak - San Jose CA, US
Duc Quang Bui - Grand Prairie TX, US
Abhijeet Chachad - Plano TX, US
Kai Chirca - Dallas TX, US
Naveen Bhoria - Plano TX, US
Matthew D. Pierson - Murphy TX, US
Daniel Wu - Plano TX, US
Ramakrishnan Venkatasubramanian - Plano TX, US

International Classification:

G06F 12/1045
G06F 9/30
G06F 9/345
G06F 9/38
G06F 11/00
G06F 11/10
G06F 9/32
G06F 12/0875
G06F 12/0897
G06F 12/0862
G06F 12/1009

Abstract:

Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.

US Patent:

20210109868, Apr 15, 2021

Filed:

Oct 12, 2020

Appl. No.:

17/068730

Inventors:

- Dallas TX, US
Joseph Raymond Michael ZBICIAK - San Jose CA, US
Kai CHIRCA - Dallas TX, US
Daniel Brad WU - Plano TX, US

International Classification:

G06F 12/1027
G06F 12/1009
G06F 12/0882
G06F 12/0891

Abstract:

A method includes receiving, by a memory management unit (MMU) comprising a translation lookaside buffer (TLB) and a configuration register, a request from a processor core to directly modify an entry in the TLB. The method also includes, responsive to the configuration register having a first value, operating the MMU in a software-managed mode by modifying the entry in the TLB according to the request. The method further includes, responsive to the configuration register having a second value, operating the MMU in a hardware-managed mode by denying the request.

US Patent:

20190146790, May 16, 2019

Filed:

Dec 20, 2018

Appl. No.:

16/227238

Inventors:

- Dallas TX, US
Joseph Zbiciak - San Jose CA, US
Duc Quang Bui - Grand Prairie TX, US
Abhijeet Chachad - Plano TX, US
Kai Chirca - Dallas TX, US
Naveen Bhoria - Plano TX, US
Matthew D. Pierson - Murphy TX, US
Daniel Wu - Plano TX, US
Ramakrishnan Venkatasubramanian - Plano TX, US

International Classification:

G06F 9/30
G06F 9/345
G06F 9/38
G06F 11/10
G06F 9/32
G06F 12/0875
G06F 12/0897
G06F 11/00

Abstract:

Disclosed embodiments include a data processing apparatus having a processing core, a memory, and a streaming engine. The streaming engine is configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, and includes an address generator to generate addresses corresponding to locations in the memory, a buffer to store the data elements received from the locations in the memory corresponding to the generated addresses, and an output to supply the data elements received from the memory to the processing core as the data stream.

US Patent:

20170153890, Jun 1, 2017

Filed:

Feb 10, 2017

Appl. No.:

15/429205

Inventors:

- Dallas TX, US
Joseph Zbiciak - San Jose CA, US
Duc Quang Bui - Grand Prairie TX, US
Abhijeet A. Chachad - Plano TX, US
Kai Chirca - Dallas TX, US
Naveen Bhoria - Plano TX, US
Matthew D. Pierson - Murphy TX, US
Daniel Wu - Dallas TX, US
Ramakrishnan Venkatasubramanian - Plano TX, US

International Classification:

G06F 9/30
G06F 9/32
G06F 9/38
G06F 12/0875
G06F 12/0897

Abstract:

This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.