Darrell Richard Davis

US Patent:

20070057737, Mar 15, 2007

Filed:

Sep 14, 2005

Appl. No.:

11/226081

Inventors:

Darrell Davis - Sunrise FL, US
Mahibur Rahman - Lake Worth FL, US

International Classification:

H03L 7/00

US Classification:

331017000

Abstract:

A modulation distortion compensation system for a phase locked loop includes a compensation function () that is arranged to be coupled to a tuning voltage signal () corresponding to a tuning voltage from the phase locked loop and is configured to select a filter response from a plurality of filter responses, where the filter response corresponds to the tuning voltage. The distortion compensation system further includes a filter that is configured to distort a modulation signal in accordance with the filter response and provide a distorted signal suitable for being coupled to a modulation input of a feedback divider included with the phase locked loop, wherein the distorted signal when used by the feedback divider will facilitate modulation and compensation of a radio frequency signal provided by the phase locked loop. Various environmental measurements in addition to the tuning voltage can also be used in selecting the filter response.

US Patent:

49143212, Apr 3, 1990

Filed:

Apr 10, 1989

Appl. No.:

7/335341

Inventors:

Darrell E. Davis - Sunrise FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1908

US Classification:

307446

Abstract:

A BIMOS lever convertor (10) comprises a differential circuit having a common biasing network (14). A MOS transistor (16) in one portion of the differential circuit receives a MOS level input signal (32) and provides an ECL level output signal (34). The other portion of the differential circuit includes a bipolar transistor (18) that is biased by the MOS transistor (16). The bipolar transistor (18) operates to provide a complementary ECL level output signal (34') so as to provide a single ended MOS to differential ECL interface suitable for integration in an I. C.

US Patent:

44019505, Aug 30, 1983

Filed:

Dec 5, 1980

Appl. No.:

6/213285

Inventors:

Darrell E. Davis - Sunrise FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 345

US Classification:

330255

Abstract:

A low-voltage, complementary symmetry amplifier arrangement is disclosed which functions effectively on supply voltages down to one volt DC. The amplifier is especially suited for audio processing applications in hand-held personal electronics apparatus, such as pocket radio receivers. The circuit configuration is easily implemented in integrated circuit form and operates efficiently on class B operation with its attendant advantages. The amplifier arrangement is characterized by the use of current sources in the collector and emitter circuits of a differential amplifier and thereby employs current ratios instead of the more conventional voltage levels to selectively control the conduction of associated output devices.

US Patent:

61007307, Aug 8, 2000

Filed:

Nov 30, 1998

Appl. No.:

9/201015

Inventors:

Darrell Eugene Davis - Sunrise FL
Scott Robert Humphreys - Boynton Beach FL

Assignee:

Motorola - Schaumburg IL

International Classification:

H03B 1900

US Classification:

327117

Abstract:

A prescaler system (100) has a prescaler circuit (102) coupled to a divider (104), wherein the divider includes an improved dynamic flip flop divider (118). The divider (118) includes a TSPC nine-transistor D-flip-flop (10). The divider further includes a tenth transistor such as N channel device (41) having a source coupled to ground (43), a drain coupled to a junction between a drain of a P channel device (34) and a drain of another N channel device (37). The divider also includes an eleventh transistor such as N channel device (42) having a source coupled to ground and a drain coupled to a junction between the drain of a P channel device (35) and the drain of a N channel device (39), the junction providing a feedback signal to a N channel device (36), wherein the eleventh transistor further has a gate coupled to the output signal (/Q. sub. A).

US Patent:

60648694, May 16, 2000

Filed:

Mar 2, 1998

Appl. No.:

9/033011

Inventors:

Darrell Eugene Davis - Sunrise FL
Scott Robert Humphreys - Boynton Beach FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04Q 730

US Classification:

455260

Abstract:

A synthesizer (100) is used for generating a plurality of synthesized clock signals (128, 156). The synthesizer includes a clock source (102) for generating a common frequency reference signal (103), and a clock generator (104) coupled to the common frequency reference signal for generating a plurality of generated clock signals (106, 108), wherein each of the plurality of generated clock signals is offset from each other by a predetermined phase offset (189, 192). In addition, the synthesizer includes a plurality of PLLs (Phase Locked Loops) (166-168) for generating a selected one of the plurality of synthesized clock signals, wherein each of the plurality of PLLs is coupled to, and operates from, a corresponding one of the plurality of generated clock signals, and wherein the predetermined phase offset between each of the plurality of generated clock signals is known to suppress noise between the plurality of PLLs operating therefrom.

US Patent:

59399112, Aug 17, 1999

Filed:

Mar 5, 1998

Appl. No.:

9/033619

Inventors:

Scott Robert Humphreys - Boynton Beach FL
Darrell Eugene Davis - Sunrise FL
Barry W. Herold - Delray Beach FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03L 706

US Classification:

327147

Abstract:

A low input prescaler (800) that is responsive to input signals having low amplitude alternating current (AC) components includes a switched tunable prescaler (280) that generates a prescaler output signal (221) having a prescaler output frequency during an operational state of the prescaler and having a free-running frequency that is responsive to a tuning control signal (216) during a tuning state of the prescaler. A frequency comparator (235) generates a comparator output in response to a difference between a reference frequency and the prescaler output frequency. A prescaler tuner (290, 390) adjusts the tuning control signal in response to the comparator output during the tuning state to minimize the difference between the reference frequency and the prescaler output frequency, and holds the tuning control signal during the operational state. The prescaler is used in phase lock loops (200, 400, 600) and other circuits.

US Patent:

49947680, Feb 19, 1991

Filed:

Mar 26, 1990

Appl. No.:

7/499102

Inventors:

Wayne P. Shepherd - Sunrise FL
Darrell E. Davis - Sunrise FL
Frederick L. Martin - Gainesville FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03C 309

US Classification:

332127

Abstract:

A frequency synthesizer (10) for providing a modulated output signal (fo) includes a reference frequency signal (fr) and a voltage controlled oscillator (14). For dividing the frequency of the output signal from the voltage controlled oscillator (14) by a divisor, a programmable divider (16) is coupled to the output of the voltage controlled oscillator (14). To produce a phase-locked loop in which the frequency of the output signal from the voltage controlled oscillator (14) is equal to the frequency of the reference frequency (fr) signal multiplied by the divisor, a phase detector (12 ) having a first input coupled to the reference frequency signal (fr), a second input coupled to the output of the programmable divider (16), and an output coupled to the input of the voltage controlled oscillator (14) is also provided. A first integrator (24) for integrating a modulating signal provides an integrated signal and a first control signal. Similarly, a second integrator (25) coupled to the first integrator (24) for integrating the integrated signal provides a second control signal.

US Patent:

50067303, Apr 9, 1991

Filed:

Sep 21, 1990

Appl. No.:

7/586321

Inventors:

Darrell E. Davis - Sunrise FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1902
H03K 19086
H03K 190175

US Classification:

307446

Abstract:

A BIMOS logic gate (10) comprises a differential circuit having a common biasing network (14). A MOS transistor (16) in one portion of the differential circuit receives a MOS level input signal (36) and provides an ECL level output signal (34). A bipolar transistor (20) is biased by a complementary ECL level input signal 32'. The other portion of the differential circuit includes a bipolar transistor (30) that is biased by an ECL level input signal 32. The emitter coupled transistors 20 and 30, receiving complementary ECL level inputs, along with the MOS transistor 36, receiving MOS level inputs, combine to provide logic functions with ECL level outputs 34 and 34'.