Darrell D Hill

US Patent:

57007012, Dec 23, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/472081

Inventors:

Darrell Hill - Plano TX
Shou-Kong Fan - Taiwan, CN
Ali Khatibzadeh - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21265

US Classification:

437 31

Abstract:

This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.

US Patent:

60233362, Feb 8, 2000

Filed:

Dec 3, 1997

Appl. No.:

8/984223

Inventors:

Darrell G. Hill - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01B 1100

US Classification:

356399

Abstract:

A method and apparatus for accurate automated alignment of semiconductor chips (12,14) or thin-film networks includes forming a plurality of vias (16-19,22-25) in each integrated circuit element in respective locations, and moving the integrated circuit elements to bring the corresponding vias into alignment. In one embodiment, the integrated circuit elements (12,14) are moved by inserting a plurality of spindles (36-39) into respective vias in the integrated circuit elements to align the integrated circuit elements. In another embodiment, the integrated circuit elements (40,42) are moved by providing a source of light (48) on one side of the integrated circuit elements and a light sensor (50) on another side of the integrated circuit elements, and moving the integrated circuit elements to maximize the amount of light traversing the vias (44,46). To enable precision alignment of the integrated circuit elements, the vias may be formed with diameter less than 50. mu. m.

US Patent:

6159816, Dec 12, 2000

Filed:

Jun 7, 1995

Appl. No.:

8/482034

Inventors:

Darrell G. Hill - Plano TX
Timothy S. Henderson - Richardson TX
William U. Liu - Plano TX
Hin-Fai Chau - Plano TX
Damian Costa - Dallas TX
Ali Khatibzadeh - Plano TX

Assignee:

TriQuint Semiconductor Texas, Inc. - Hillsboro OR

International Classification:

H01L 21331

US Classification:

438309

Abstract:

A bipolar transistor includes a passivating layer of material 40 in the base structure 42 that serves to cover the extrinsic base region of the transistor. The passivating layer 40 is formed of a material having a wider bandgap than the base layer 44, and is heavily doped with the same doping type (n or p) as the base layer. The invention is advantageous in that the base contacts 48 of the device are made directly to the passivating layer 40 and are not in direct contact with the base layer 44. This eliminates the need for alloyed contacts and the concomitant reliability problems associated with spiking contacts. In addition, the invention is completely compatible with self-aligned production techniques.

US Patent:

52780830, Jan 11, 1994

Filed:

Oct 16, 1992

Appl. No.:

7/962433

Inventors:

Darrell G. Hill - Plano TX
William U. Liu - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2970

US Classification:

437 31

Abstract:

Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.

US Patent:

60283483, Feb 22, 2000

Filed:

Nov 30, 1993

Appl. No.:

8/159648

Inventors:

Darrell G. Hill - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27148
H01L 29768
H01L 23495

US Classification:

257666

Abstract:

A frontside ground plane (306) integrated circuit with backside contacts (312) plus optional passive components such as microstrip (308) and capacitors. The frontside ground plane provides direct heat dissipation from active junctions such as heterojunction and field effect transistors.

US Patent:

57100683, Jan 20, 1998

Filed:

Jun 7, 1995

Appl. No.:

8/476832

Inventors:

Darrell G. Hill - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21265

US Classification:

437415M

Abstract:

A frontside ground plane (306) integrated circuit with backside contacts (312) plus optional passive components such as microstrip (308) and capacitors. The frontside ground plane provides direct heat dissipation from active junctions such as heterojunction and field effect transistors.

US Patent:

55258182, Jun 11, 1996

Filed:

Aug 3, 1994

Appl. No.:

8/285601

Inventors:

Darrell G. Hill - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 310328
H01L 31109
H01L 2906

US Classification:

257197

Abstract:

This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semi-conducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.

US Patent:

54340918, Jul 18, 1995

Filed:

Oct 7, 1994

Appl. No.:

8/320792

Inventors:

Darrell Hill - Plano TX
Ali Khatibzadeh - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21265

US Classification:

437 31

Abstract:

This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.

Address:

3708 Pecos St, Fort Worth, TX 76119

Phone:

(972)2640365

VIN:

1FMYU02Z77KB60132

Make:

FORD

Model:

ESCAPE

Year:

2007