David M Bingham

US Patent:

48977748, Jan 30, 1990

Filed:

Nov 14, 1988

Appl. No.:

7/271160

Inventors:

David Bingham - San Jose CA
Charles M. Allen - Sunnyvale CA

Assignee:

Maxim Integrated Products - Sunnyvale CA

International Classification:

0 2M 725

US Classification:

363 61

Abstract:

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as a voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the circuit.

US Patent:

59888199, Nov 23, 1999

Filed:

Feb 17, 1998

Appl. No.:

9/024859

Inventors:

Sui Ping Shieh - Los Altos CA
Pirooz Parvarandeh - Los Altos CA
David Bingham - Mount Hamilton CA

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

G05F 110

US Classification:

357537

Abstract:

An interface output stage includes a pull-up circuit and a pull-down circuit connected to a positive power supply signal line having a first voltage, an output signal line having an output voltage and a negative power supply signal line having a second voltage. The pull-up circuit includes a single output transistor and a body snatcher circuit, both interconnected between the positive power supply signal line and the output signal line. The body snatcher circuit ties the bodies of the output transistor and the transistors forming the body snatcher circuit to either the first voltage or the output voltage. The pull-down circuit is designed generally similar to the pull-up circuit to tie bodies of its transistors to either the output voltage or the second voltage.

US Patent:

41952669, Mar 25, 1980

Filed:

Jun 1, 1978

Appl. No.:

5/911496

Inventors:

David Bingham - Los Altos CA

Assignee:

Intersil, Inc., - Cupertino CA

International Classification:

H03F 102

US Classification:

330 9

Abstract:

A system or circuit for signal level translation by information storage on multiple capacitors subjected to commutation at a frequency higher than the highest preserved frequency component of the signal. Continuous level translation of information, such as successive voltage levels, is accomplished with very small error. The invention is particularly applicable to instrumentation amplifiers for example, wherein differential input voltages are required to be referenced to some other base voltage such as zero or ground voltage.

US Patent:

46791345, Jul 7, 1987

Filed:

Jun 25, 1986

Appl. No.:

6/878233

Inventors:

David Bingham - San Jose CA
Charles M. Allen - Sunnyvale CA

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H02M 318

US Classification:

363 61

Abstract:

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as a voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the circuit.

US Patent:

47775807, Oct 11, 1988

Filed:

Oct 16, 1986

Appl. No.:

6/920891

Inventors:

David Bingham - San Jose CA

Assignee:

Maxim Integrated Products - Sunnyvale CA

International Classification:

H02M 7217

US Classification:

363127

Abstract:

A full-wave rectifier circuit is disclosed having two AC input terminals each having connected to it the anode end of a diode equivalent device. The cathode ends of each of the diode equivalent devices are connected together to a positive DC output terminal. Each AC input terminal also has connected to it one end of a switching device. The other ends of each of the switching devices are connected together to a negative DC output terminal. The control means of the switching devices are connected such that only one conducts during any AC half cycle to provide a return path from the negative DC output terminal to the proper one of the two AC input terminals.

US Patent:

47002867, Oct 13, 1987

Filed:

Oct 16, 1986

Appl. No.:

6/924933

Inventors:

David Bingham - San Jose CA

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H02M 7217

US Classification:

363127

Abstract:

An integrated off-line half-wave rectifier commonly connected to one side of the AC line at one of its output terminals is disclosed. An equivalent diode device passes current to the output during a positive AC input half cycle. A comparator senses the negative half cycle and turns on a switching device to conduct current between the two AC input terminals during that cycle.

US Patent:

44737572, Sep 25, 1984

Filed:

Dec 8, 1981

Appl. No.:

6/328518

Inventors:

Jules C. Farago - San Jose CA
Andrew M. Wolff - Mountain View CA
David Bingham - Los Altos CA

Assignee:

Intersil, Inc. - Cupertino CA

International Classification:

H01L 2700

US Classification:

307127

Abstract:

A circuit which accepts an input signal of either positive or negative polarity and produces an output signal having an open circuit voltage similar in amplitude to the input signal amplitude but having a defined polarity. A plurality of switching elements, preferably MOS transistors, are connected in a bridge circuit, the bridge circuit having a pair of input terminals responsive to the input signal and a pair of output terminals for providing the output signal, the switching elements being connected between the input and output terminals. Each of the switching elements has a control input connected to one of the input terminals whereby each of the switching elements automatically opens or closes in response to the polarity of the input signal to maintain the defined polarity of the output signal.

US Patent:

48128910, Mar 14, 1989

Filed:

Dec 17, 1987

Appl. No.:

7/133958

Inventors:

David Bingham - San Jose CA

Assignee:

Maxim Integrated Products - Sunnyvale CA

International Classification:

H01L 2972
H01L 2702
H03K 326

US Classification:

357 35

Abstract:

A bipolar lateral pass-transistor is disclosed for use in MOS integrated circuits. The transistor includes a semiconductor substrate of a first conductivity type covered by an epitaxial layer, a first region of a second conductivity type disposed in the epitaxial layer at a first doping level to a depth of less than the depth of said epitaxial layer, a second region of said conductivity type spaced apart from and surrounding said first region and extending approximately the entire depth of said epitaxial layer having a doping level less than the first doping level and a third region of said second conductivity type spaced apart from and surrounding said second region and extending approximately the entire depth of said epitaxial layer having said first doping level at the surface of said epitaxial layer and said second doping level extending approximately to the bottom of said epitaxial layer. In another aspect of the present invention the bipolar lateral pass-transistor is connected to a voltage source and MOS devices also disposed on the surface of the semiconductor substrate are powered by a voltage which is less than the voltage applied to the lateral pass-transistor, in order to prevent desirable forward biasing of parasitic PN junctions.