David Jay Bird

US Patent:

20070100825, May 3, 2007

Filed:

Nov 1, 2005

Appl. No.:

11/267784

Inventors:

Russell Guenthner - Glendale AZ, US
Clinton Eckard - McMinnville TN, US
David Bird - Phoenix AZ, US
John Heath - Glendale AZ, US

International Classification:

G06F 7/00

US Classification:

707007000

Abstract:

A process for sorting large files or structures is disclosed where improved performance is achieved by reducing the work involved and the time required to do record key comparisons. The reduction is achieved by transposing and saving the key data from each record into a representative form that can be more quickly compared each time the key comparison is required. In addition the process uses pointers to avoid the processing time to exchange records larger than one word in memory. The representation of the key data is optimized and aligned for comparison by word based computer instructions which are typically faster than byte based instructions. The process is optimized for word sizes and instructions which handle words larger than four bytes and in particular for machines and instructions with 64-bit or larger word sizes such as the Intel Itanium series processors.

US Patent:

39744027, Aug 10, 1976

Filed:

Mar 26, 1975

Appl. No.:

5/562329

Inventors:

Darrell L. Fett - Scottsdale AZ
David A. Bird - Phoenix AZ
Jerry L. Rauser - Crystal MN

Assignee:

Honeywell Information Systems, Inc. - Phoenix AZ

International Classification:

H03K 114
H03K 1908

US Classification:

307264

Abstract:

A logic level translator utilizes a TTL logic gate, a current switch, and a clamp circuit to convert CML level binary signals into TTL level binary signals. The translator provides isolation between the TTL ground and the CML ground in order to reduce noise in the CML portion of the circuit. The clamp circuit prevents a switching transistor in the current switch from reaching saturation, thereby increasing the speed of operation of the translator. A portion of the current switch provides a quick pulldown of a switching transistor in the TTL circuit to reduce noise in the TTL circuit.

US Patent:

39596664, May 25, 1976

Filed:

Jul 1, 1974

Appl. No.:

5/484513

Inventors:

Darrell L. Fett - Scottsdale AZ
David A. Bird - Phoenix AZ

Assignee:

Honeywell Information Systems, Inc. - Waltham MA

International Classification:

H03K 1908
H03K 502
H03K 508
H03K 5156

US Classification:

307208

Abstract:

A logic level translator uses a current switch, a current source and a plurality of cathode followers to convert T. sup. 2 L and DTL level binary signals into CML and ECL level binary signals. The translator provides isolation between the T. sup. 2 L ground and the CML ground so that noise in the CML signals is reduced.

US Patent:

54264359, Jun 20, 1995

Filed:

Oct 28, 1988

Appl. No.:

7/263832

Inventors:

Gerald J. Moore - Mesa AZ
David G. Bird - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G01S 1308

US Classification:

342 68

Abstract:

An open loop proximity detector is contemplated which receives a Doppler frequency when a target is first detected, and predicts a specific fuzing Doppler frequency. The detector continues to transmit and receive electromagnetic waves and sends a detonating signal to the fuze when the predicted fuzing Doppler frequency is received by the detector. The Doppler frequency of the first, or front surface in a forward moving direction of the target is received and is used to detonate the fuze. Thus the ideal surface of the target, the front surface, detonates the fuze and Doppler frequencies from other surfaces of the target are not allowed to interfere with the detonating process.