David A Bowman

US Patent:

58128220, Sep 22, 1998

Filed:

Dec 19, 1995

Appl. No.:

8/574821

Inventors:

David W. Selway - Phoenix AZ
David A. Bowman - Glendale AZ
Donald R. Kesner - Phoeniz AZ
James H. Phillips - Phoenix AZ

International Classification:

G06F 110

US Classification:

395500

Abstract:

A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. When the two systems are split, each system is controlled by the oscillator signal generated by its own CGD unit. When the two systems are merged, one oscillator is designated as master, and its output is employed to derive the clock and definer signals on both sides of the redundant system. Special logic included in each CGD unit ensures that the change from master to slave (or slave to master) operation is performed without error. This special logic includes circuitry which places a temporary hold at a predetermined logic level on the local oscillator signal, which is in use when the switch is made, when the local clock and definer signals are both at the predetermined logic level. The hold continues until the oscillator which is to "take over" is also at the predetermined logic level.

US Patent:

57403503, Apr 14, 1998

Filed:

Mar 18, 1997

Appl. No.:

8/823663

Inventors:

Leonard Rabins - Scottsdale AZ
David A. Bowman - Glendale AZ
David W. Selway - Phoenix AZ
Clark D. McCaslin - Phoenix AZ
Donald R. Kesner - Phoenix AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 1300
G06F 1500

US Classification:

39518208

Abstract:

A reconfigurable computer system which includes two computer subsystems, corresponding lines of the system busses of the two computer subsystems being interconnected by solid state switches. Each of the computer subsystems includes a control component, a service processor, which when an error is detected that would render the subsystem inoperative, causes the solid state switches to open to sever the connection between the system busses of the two computer subsystems so that the computer subsystem that has not suffered such a failure can continue to operate. A communication link is also established between the two service processors. Either, or both, service processors can sever the link between them.

US Patent:

60553626, Apr 25, 2000

Filed:

Mar 29, 1996

Appl. No.:

8/625664

Inventors:

Donald R. Kesner - Phoenix AZ
David W. Selway - Phoenix AZ
David A. Bowman - Glendale AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 1500
G06F 1134

US Classification:

395180

Abstract:

A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. The clock and definer signals of each system are used internally and are also sent to the other system. When the two systems are split, phase locked loops in each system are disabled, and each system is controlled by a precision oscillator in its own CGD unit When the two systems are merged, one CGD is designated as master and remains under control of its internal oscillator. The clock and definer signals of the master system are employed in the slave system to derive a signal which is used as the reference input to the slave system's phase locked loop from which the slave system's clock and definer signals are developed. Preferably, dual flip-flop phase detector type phase locked loops are employed. For higher frequency operation, it is desirable to incorporate certain correction circuitry which minimizes phase offset at apparent phase lock which is an inherent characteristic of this type of phase locked loop.

US Patent:

55839983, Dec 10, 1996

Filed:

Jan 26, 1993

Appl. No.:

8/009366

Inventors:

David A. Bowman - Glendale AZ

Assignee:

Bull HN Information Systems Inc. - Phoenix AZ

International Classification:

H01R 900

US Classification:

395280

Abstract:

In order to increase the information exchange speed among the several transaction members or subsystems organized around a bus carried on a backpanel, all lines of the bus are isolated, using CMOS switches, from the stub to each transaction member which is not instantaneously required for information exchange. The CMOS switches are physically placed as close as practical to the junction of each individual stub to the bus proper. This is achieved by placing the integrated circuits containing the CMOS switches on each subsystem circuit board proximate the male-edge-connector-to-female-edge-connector regions at which the junctions between the bus proper and the stubs are established. Preferably, the CMOS switch integrated circuits are emplaced on the backpanel itself proximate the edge connector regions communicating with each of the subsystems.

US Patent:

57457425, Apr 28, 1998

Filed:

Dec 19, 1995

Appl. No.:

8/574804

Inventors:

David W. Selway - Phoenix AZ
David A. Bowman - Glendale AZ
Donald R. Kesner - Phoenix AZ
James H. Phillips - Phoenix AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 110

US Classification:

395556

Abstract:

A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. When the two systems are split, each system is controlled by the clock and definer signals generated by its own CGD unit. When the two systems are merged, one CGD unit is designated as master, and its clock and definer signals drives both sides of the redundant system. Special logic included in each CGD unit ensures that the change from master to slave (or slave to master) operation is performed without error. This special logic includes circuitry which places a temporary hold at a predetermined logic level on the local clock and definer signals, which are in use when the switch is made, when the local clock and definer signals are both at the predetermined logic level. The hold continues until the clock and definer signals which are to "take over" are also at the predetermined logic level.

US Patent:

40064670, Feb 1, 1977

Filed:

Nov 14, 1975

Appl. No.:

5/632127

Inventors:

David A. Bowman - Glendale AZ

Assignee:

Honeywell Information Systems, Inc. - Phoenix AZ

International Classification:

G11C 1140

US Classification:

340173R

Abstract:

A memory organization system is disclosed which comprises an improved, bit-organized RAM system. The invention substantially limits errors within the RAM system such that they are error-correctible by existing error detection and correction means. Commonly available RAMs are organized on a logic board such that each bit of a word being addressed is provided by a different RAM chip and is driven by a distinct driver. In this manner a malfunction in either a chip or a driver circuit results in only a one-bit error per word and overall system performance is also improved.