David W Burnette

US Patent:

6817007, Nov 9, 2004

Filed:

Apr 19, 2002

Appl. No.:

10/126911

Inventors:

David Gaines Burnette - Tigard OR 97224
Peter Pius Gutberlet - Wilsonville OR 97070

International Classification:

G06F 1750

US Classification:

716 18, 716 1, 716 2, 716 16

Abstract:

A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate loop configuration information without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find loops. The loops are then listed in a graphical user interface (GUI) in hierarchical fashion. The GUI also lists loop configuration information associated with the loops, such as loop frequency, loop unrolling and loop pipelining. The GUI allows the designer to modify the loop configuration information without having to update the source code description. Upon completion of modifying the loop configuration information, the designer saves the changes illustrated in the GUI and such changes are effectuated by automatically updating the synthesis intermediate format.

US Patent:

7168059, Jan 23, 2007

Filed:

Apr 19, 2002

Appl. No.:

10/126913

Inventors:

Bryan Darrell Bowyer - Newberg OR, US
David Gaines Burnette - Tigard OR, US
Ian Andrew Guyler - Wilsonville OR, US

International Classification:

G06F 17/50

US Classification:

716 18, 716 1, 716 4, 716 5, 703 13, 703 14

Abstract:

A tool is disclosed that allows a hardware designer using a behavioral synthesis tool to view a calculated execution time for a group of related loops identified in source code describing a hardware design circuit. Further, a designer can then interactively unroll and/or pipeline a selected loop without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop design easily and see the results of the new loop configuration without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view the relative loop execution time of the circuit to better determine whether the design is acceptable. Additionally, the designer can execute an area-versus-latency analysis, and, if the analysis is not satisfactory, the designer can unroll and or pipeline selected loops using the GUI.

US Patent:

7496864, Feb 24, 2009

Filed:

Aug 30, 2004

Appl. No.:

10/930235

Inventors:

David Gaines Burnette - Tigard OR, US
Peter Pius Gutberlet - Wilsonville OR, US

International Classification:

G06F 17/50

US Classification:

716 2, 716 1, 716 11, 716 18

Abstract:

A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate loop configuration information without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find loops. The loops are then listed in a graphical user interface (GUI) in hierarchical fashion. The GUI also lists loop configuration information associated with the loops, such as loop frequency, loop unrolling and loop pipelining. The GUI allows the designer to modify the loop configuration information without having to update the source code description. Upon completion of modifying the loop configuration information, the designer saves the changes illustrated in the GUI and such changes are effectuated by automatically updating the synthesis intermediate format.

US Patent:

8146030, Mar 27, 2012

Filed:

Jan 13, 2009

Appl. No.:

12/353210

Inventors:

David Gaines Burnette - Tigard OR, US
Peter Pius Gutberlet - Wilsonville OR, US

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 17/50

US Classification:

716104, 716113, 716132

Abstract:

A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate loop configuration information without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find loops. The loops are then listed in a graphical user interface (GUI) in hierarchical fashion. The GUI also lists loop configuration information associated with the loops, such as loop frequency, loop unrolling and loop pipelining. The GUI allows the designer to modify the loop configuration information without having to update the source code description. Upon completion of modifying the loop configuration information, the designer saves the changes illustrated in the GUI and such changes are effectuated by automatically updating the synthesis intermediate format.

US Patent:

6611952, Aug 26, 2003

Filed:

Apr 20, 2001

Appl. No.:

09/839376

Inventors:

Shiv Prakash - Wilsonville OR 97070
David Gaines Burnette - Tigard OR 97224
Simon Waters - Tualatin OR 97062

International Classification:

G06F 1750

US Classification:

716 18, 716 11, 716 5

Abstract:

A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory resources without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find arrays for each process. The arrays are then listed in a graphical user interface (GUI). The GUI allows the designer to create memory resources, specifying the type of memory, the packing mode, etc. The designer can then drag and drop the array variables listed in the GUI onto the memory resources. Upon completion of modifying the memory allocation, the designer saves the changes illustrated in the GUI and such changes are effectuated by automatically updating the synthesis intermediate format.

US Patent:

20210322461, Oct 21, 2021

Filed:

Apr 15, 2020

Appl. No.:

16/849138

Inventors:

- Athens OH, US
David BURNETTE - Lancaster OH, US

International Classification:

A61K 33/00
C08J 3/24
A61P 27/02

Abstract:

A method of cross-linking collagen comprises generating reactive species from a non-thermal plasma and delivering the reactive species to a collagen-containing target to induce collagen cross-linking. In a specific embodiment, the reactive species can be a reactive oxygen species, for example singlet oxygen. A method of cross-linking collagen comprises generating reactive oxygen species from a non-thermal plasma and delivering the reactive species to a collagen-containing target to induce collagen cross-linking, wherein the non-thermal plasma is generated from a non-flammable gas medium comprising an inert buffer gas, the reactive oxygen species is selected from the group consisting of a superoxide ion radical, hydroxyl radical, peroxide, hydrogen peroxide, organic peroxide, or a combination thereof, and the collagen-containing target is corneal tissue and wherein the collagen cross-linking induces cross-linking within and between collagen fibers in the corneal tissue.