David Mark Carey

US Patent:

53791916, Jan 3, 1995

Filed:

Jun 9, 1994

Appl. No.:

8/257235

Inventors:

David H. Carey - Austin TX
Barry H. Whalen - Austin TX

Assignee:

Microelectronics and Computer Technology Corporation - Austin TX

International Classification:

H05K 702
H01R 909

US Classification:

361777

Abstract:

An peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.

US Patent:

52726002, Dec 21, 1993

Filed:

Sep 2, 1992

Appl. No.:

7/939228

Inventors:

David H. Carey - Austin TX

Assignee:

Microelectronics and Computer Technology Corporation - Austin TX

International Classification:

H05K 114

US Classification:

361792

Abstract:

The invention relates to an electrical interconnect device with power and ground lines interwoven about signal line layers and capacitive vias between signal layers so as to make efficient use of otherwise undedicated area between signal lines and signal layers and to reduce or eliminate the need for separate power and ground layers while providing decoupling capacitance within the wiring structure.

US Patent:

51328780, Jul 21, 1992

Filed:

Apr 25, 1989

Appl. No.:

7/344534

Inventors:

David H. Carey - Austin TX

Assignee:

Microelectronics and Computer Technology Corporation - Austin TX

International Classification:

H05K 111

US Classification:

361410

Abstract:

A customizable circuit using a programmable interconnect and a compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form along diagonal lines having a pitch determined by the basic wire segment length. The terminal ends of each of these segments are positioned in a plane such that the segments may be connected by short lengths to form the desired interconnect. The links which join the line segments represent the customization of the otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the intergrated circuit chips to the programmable interconnect. Also disclosed are methods for forming the interconnect and the TAB chip bonding design.

US Patent:

51734427, Dec 22, 1992

Filed:

Mar 24, 1992

Appl. No.:

7/857011

Inventors:

David H. Carey - Austin TX

Assignee:

Microelectronics and Computer Technology Corporation - Austin TX

International Classification:

H01L 21283
H01L 21306

US Classification:

437173

Abstract:

Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.

US Patent:

52197875, Jun 15, 1993

Filed:

Feb 24, 1992

Appl. No.:

7/840428

Inventors:

David H. Carey - Austin TX
Douglass A. Pietila - Puyallup WA
David M. Sigmond - Austin TX

Assignee:

Microelectronics and Computer Technology Corporation - Austin TX

International Classification:

H01L 21283
H01L 21306

US Classification:

437187

Abstract:

Trenching techniques for forming a channel partially through and a via completely through the insulating layer of a substrate are disclosed. With additional steps the channel can form an electrically conductive line, an electrode of an integrated capacitor, or an optical waveguide.

US Patent:

52406717, Aug 31, 1993

Filed:

Jun 1, 1992

Appl. No.:

7/891029

Inventors:

David H. Carey - Austin TX

Assignee:

Microelectronics And Computer Technology Corporation - Austin TX

International Classification:

B22F 704
H01K 322

US Classification:

419 9

Abstract:

A method of forming recessed patterns in insulators is described. One embodiment of the invention is directed to ceramic green sheet fabrication by providing a sculptured plastic tape mold which includes a floor, a plurality of sidewalls adjacent to and extending above the floor and a plurality of protrusions on and extending above the floor, casting a ceramic slurry into the mold such that the slurry contacts the floor, the sidewalls and the protrusions, and drying the slurry so as to produce a ceramic green sheet with a recessed pattern that replicates the shapes of the protrusions. The ceramic green sheet may be removed from the mold and filled with a conductor before firing; alternatively, the ceramic green sheet can be fired before removing the mold to form a rigid ceramic substrate which is then filled with a conductor.

US Patent:

51651661, Nov 24, 1992

Filed:

Sep 9, 1991

Appl. No.:

7/739344

Inventors:

David H. Carey - Austin TX

Assignee:

Microelectronics and Computer Technology Corporation - Austin TX

International Classification:

H05K 302

US Classification:

29847

Abstract:

A customizable circuit using a programmable interconnect and a compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form along diagonal lines having a pitch determined by the basic wire segment length. The terminal ends of each of these segments are positioned in a plane such that the segments may be connected by short lengths to form the desired interconnect. The links which join the line segments represent the customization of the otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the integrated circuit chips to the programmable interconnect. Also disclosed are methods for forming the interconnect and the TAB chip bonding design.

US Patent:

50396285, Aug 13, 1991

Filed:

Feb 12, 1990

Appl. No.:

7/479487

Inventors:

David H. Carey - Austin TX

Assignee:

Microelectronics & Computer Technology Corporation - Austin TX

International Classification:

H01L 2316

US Classification:

437183

Abstract:

A substrate for attaching electrical devices having an interconnect wiring structure and a support for the interconnect, the support having a number of vias, or throughholes, extending therethrough and electrically connected to the interconnect. The substrate allows for attachment of the electrical devices on the side of the support opposite the interconnect at the vias, rather than on the interconnect itself. By so doing, the chips can be packed more density since the area between the chips normally reserved for engineering change pads, test pads and the like is not required, these functions being performed on the interconnect on the opposite side of the substrate.