David Shu Chan

US Patent:

6506097, Jan 14, 2003

Filed:

Jan 16, 2001

Appl. No.:

09/764733

Inventors:

Bret W. Adams - Sunnyvale CA
Boguslaw A. Swedek - San Jose CA
Rajeev Bajaj - Fremont CA
Savitha Nanjangud - San Jose CA
Andreas Norbert Wiswesser - Mountain View CA
Stan D. Tsai - Fremont CA
David A. Chan - Sunnyvale CA
Fred C. Redeker - Fremont CA
Manoocher Birang - Los Gatos CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B24B 100

US Classification:

451 5, 451 6, 451 9, 451 36, 451 57, 438692

Abstract:

An optical monitoring system for a two-step polishing process which generates a reflectance trace for each of plurality of radial zones. The CMP apparatus may switch from a high-selectivity slurry to a low-selectivity slurry when any of the reflectance traces indicate initial clearance of the metal layer, and polishing may halt when all of the reflectance traces indicate that oxide layer has been completely exposed.

US Patent:

6586814, Jul 1, 2003

Filed:

Dec 11, 2000

Appl. No.:

09/735084

Inventors:

Rajiv Patel - San Jose CA
David Chan - San Jose CA
Arvind Kamath - Mountain View CA
Ken Rafftesaeth - San Jose CA
Venkatesh P. Gopinath - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2900

US Classification:

257506, 257510, 438221, 438296, 438424

Abstract:

A shallow isolating trench is formed in a semiconductor wafer between active component areas to electrically isolate the active components from each other. The isolating trench is primarily formed of an insulating material, such as an oxide, in a recess formed into the wafer. An etch resistant material, such as BTBAS nitride, is placed over the insulating material in the recess. The etch resistant material protects the insulating material from erosion due to subsequent semiconductor fabrication process steps, so the integrity of the isolating trench and the planarity of the wafer are generally maintained.

US Patent:

6632124, Oct 14, 2003

Filed:

Jan 10, 2003

Appl. No.:

10/339959

Inventors:

Bret W. Adams - Sunnyvale CA
Boguslaw A. Swedek - San Jose CA
Rajeev Bajaj - Fremont CA
Savitha Nanjangud - San Jose CA
Andreas Norbert Wiswesser - Mountain View CA
Stan D. Tsai - Fremont CA
David A. Chan - Sunnyvale CA
Fred C. Redeker - Fremont CA
Manoocher Birang - Los Gatos CA

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

B24B 100

US Classification:

451 5, 451 6, 451 9, 451 36, 451 57, 438692

Abstract:

An optical monitoring system for a two-step polishing process which generates a reflectance trace for each of plurality of radial zones. The CMP apparatus may switch from a high-selectivity slurry to a low-selectivity slurry when any of the reflectance traces indicate initial clearance of the metal layer, and polishing may halt when all of the reflectance traces indicate that oxide layer has been completely exposed.

US Patent:

6674092, Jan 6, 2004

Filed:

Jul 12, 2002

Appl. No.:

10/194578

Inventors:

Wai Lo - Lake Oswego OR
David Chan - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2358

US Classification:

257 48, 257797, 257798

Abstract:

Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and protective layer are each formed to precise tolerances. The invention also includes methods for forming a calibration standard for semiconductor metrology tools.

US Patent:

6830943, Dec 14, 2004

Filed:

Nov 4, 2003

Appl. No.:

10/702165

Inventors:

Wai Lo - Lake Oswego OR
David Chan - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2166

US Classification:

438 18, 438 17, 438 14, 438778

Abstract:

Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and protective layer are each formed to precise tolerances. The invention also includes methods for forming a calibration standard for semiconductor metrology tools.

US Patent:

6939198, Sep 6, 2005

Filed:

Dec 27, 2002

Appl. No.:

10/330687

Inventors:

Boguslaw A. Swedek - San Jose CA, US
Bret W. Adams - Sunnyvale CA, US
Sanjay Rajaram - Sunnyvale CA, US
David A. Chan - Sunnyvale CA, US
Manoocher Birang - Los Gatos CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B24B001/00
B24B049/00
B24B051/00

US Classification:

451 5, 451 6, 451 8, 451 41

Abstract:

A computer-implemented method for process control in chemical mechanical polishing in which an initial pre-polishing thickness of a substrate is measured at a metrology station, a parameter of an endpoint algorithm is determined from the initial thickness of the substrate, a substrates is polished at a polishing station, and polishing stops when an endpoint criterion is detected using the endpoint algorithm.

US Patent:

7008875, Mar 7, 2006

Filed:

Nov 24, 2003

Appl. No.:

10/721769

Inventors:

Manoocher Birang - Los Gatos CA, US
Konstantin Y. Smekalin - Pleasanton CA, US
David A. Chan - Sunnyvale CA, US

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438692, 438740

Abstract:

A CMP station can be closed loop controlled by using data obtained by an inline metrology station from a first polished wafer to affect the processing of subsequent polished wafers. The first wafer is polished and measured by the inline metrology station. The metrology station measures at various points the array dielectric thickness, field dielectric thickness, barrier residue thickness and metal residue thickness. The data is then inputted into an algorithm and polishing parameter outputs are calculated. The outputs are sent to the CMP station and used to supplement or replace the previous polishing parameters. Subsequent wafers are polished on the CMP station using the revised polishing parameters.

US Patent:

7069439, Jun 27, 2006

Filed:

Mar 3, 2000

Appl. No.:

09/936132

Inventors:

Liqun Chen - Bradley Stoke Bristol, GB
David Chan - Monte Sereno CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H04L 9/00

US Classification:

713172, 713159, 713185, 726 20, 726 26, 380251, 380255

Abstract:

Computing apparatus comprises a memory means storing the instructions of a secure process and an authentication process; a processing means arranged to control the operation of the computing apparatus including by executing the secure process and the authentication process; a user interface means arranged to receive user input and return to the user input; and an interface means for receiving a removable primary token and communication with the token. The token comprises a body supporting a token interface for communicating with the interface means, a token processor; and a token memory adapted to store token data including information for identifying the token and auxiliary token information identifying one or more authorized auxiliary tokens. The processing means is arranged to receive the identity information and the auxiliary token information from the primary token, to authenticate the toke using the authentication process and, if the token is successfully authenticated, permit a user to interact with the secure process via the user interface means. The processing means is arranged to repeatedly authenticate the primary toke and cause the computing platform to suspend interaction between the secure process and the user if authentication is not possible as a result of the removal of the primary token unless the primary token is replaced by an authorized auxiliary token.