Ahmed Amin - Allentown PA, US David L. Crouthamel - Bethlehem PA, US John W. Osenbach - Kutztown PA, US Thomas H. Shilling - Macungie PA, US Brian T. Vaccaro - Mertztown PA, US
An assembly comprises a stiffener, a circuit substrate and an IC chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers at least a portion of the first region of the stiffener, while the IC chip overlies at least a portion of each of the first and second regions of the stiffener. The assembly further comprises a signal solder bump and a thermally conductive feature. The signal solder bump contacts the IC chip and the circuit substrate. The thermally conductive feature is disposed between, and is metallurgically bonded to, the integrated circuit chip and the second region of the stiffener. The thermally conductive feature provides an efficient thermal conductivity pathway between the IC chip and the stiffener.
Encapsulating Compound Having Reduced Dielectric Constant
David Crouthamel - Bethlehem PA, US Jeffery Gilbert - Schwenksville PA, US John Osenbach - Kutztown PA, US
International Classification:
B32B003/26
US Classification:
428321100
Abstract:
An encapsulating compound includes an organic polymeric carrier material and a dielectric filler material added to the polymeric carrier material. The dielectric filler material has a dielectric constant associated therewith which is less than a dielectric constant of the polymeric carrier material. The dielectric filler material is interspersed with the polymeric carrier material such that a dielectric constant of the encapsulating compound is less than the dielectric constant of the polymeric carrier material alone.
Low Thermal Resistance Assembly For Flip Chip Applications
Mark Bachman - Sinking Spring PA, US David Crouthamel - Bethlehem PA, US
International Classification:
H01L 23/48
US Classification:
257778000
Abstract:
An assembly comprises a stiffener, a circuit substrate and an integrated circuit (IC) chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers the first region, while the IC chip overlies at least a portion of each of the first and second regions. Moreover, the assembly further comprises a plurality of first solder bumps and a plurality of second solder bumps. The first solder bumps contact both the IC chip and the circuit substrate. The second solder bumps are larger than the first solder bumps, contact the IC chip and are disposed above the second region of the stiffener.
- San Jose CA, US Suzanne M. Emerich - Mertztown PA, US David Crouthamel - Bethlehem PA, US Steven D. Cate - Los Altos CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
H01L 23/00 H01L 21/54 H01L 23/34
Abstract:
A bonding pad arrangement and method of bonding a flip-chip semiconductor device to a substrate using copper pillars and solder to join die pads on the flip-chip to substrate pads on the substrate. Each substrate pad has an offset from a respective die pad at specific temperature, the offset for each of the substrate pads is substantially the same, and the offset is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, and a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate. Alternatively, the offset for each of the substrate pads is the above-determined offset scaled as a function of a distance the respective die pad is from the centroid of the device.