David W Daly

US Patent:

20130019083, Jan 17, 2013

Filed:

Jul 11, 2011

Appl. No.:

13/179672

Inventors:

David M. Daly - Croton on Hudson NY, US
Kattamuri Ekanadham - Mohegan Lake NY, US
Michael C. Huang - Rochester NY, US
Jose E. Moreira - Irvington NY, US
Mauricio J. Serrano - Bronx NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30

US Classification:

712203, 712E09016

Abstract:

A mechanism is provided for redundant execution of a set of instructions. A redundant execution begin (rbegin) instruction to be executed by a first hardware thread on the first processor is identified in the set of instructions. The set of instructions immediately after the rbegin instruction are executed on the first hardware thread and on a second hardware thread. Responsive to both the first processor and the second processor ending execution of the set of instructions, responsive to a first set of cache lines in a first speculative store matching a second set of cache lines in a second speculative store, and responsive to a first set of register states in a first status register matching a second set of register states in a second status register, dirty lines in the first speculative store are committed thereby committing a redundant transaction state to an architectural state.

US Patent:

20130019085, Jan 17, 2013

Filed:

Jul 12, 2011

Appl. No.:

13/180634

Inventors:

David M. Daly - Croton on Hudson NY, US
Michael C. Huang - Rochester NY, US
Jose E. Moreira - Irvington NY, US
IL Park - Seoul, KR

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/38

US Classification:

712233, 712E09045

Abstract:

A mechanism is provided for reducing a penalty for executing a correct branch of a branch instruction. An execution unit in a processor of a data processing system executes a first branch of the branch instruction from a main thread of a processor and executes a second branch of the branch instruction from an assist thread of the processor. The execution unit determines whether the main thread is a correct branch of the branch instruction or the assist thread is the correct branch of the branch instruction. Responsive to the assist thread being the correct branch of the branch instruction, the execution unit pauses execution of the branch instruction on both the main thread and the assist thread. The execution unit then properly inherits a context of the main thread in order that execution of the second branch may continue.

US Patent:

20130268741, Oct 10, 2013

Filed:

Apr 4, 2012

Appl. No.:

13/439457

Inventors:

David M. Daly - Yorktown Heights NY, US
Tejas Karkhanis - White Plains NY, US
Valentina Salapura - Chappaqua NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/02

US Classification:

711165, 711E12002

Abstract:

A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.

US Patent:

20160364270, Dec 15, 2016

Filed:

Aug 26, 2016

Appl. No.:

15/248025

Inventors:

- Armonk NY, US
David M. Daly - Croton on Hudson NY, US
Brian R. Prasky - Campbell Hall NY, US
Vijayalakshmi Srinivasan - New York NY, US

International Classification:

G06F 9/50
G06F 9/48
G06F 12/0891
G06F 12/0897
G06F 12/123
G06F 12/0862

Abstract:

Embodiments relate to thread-based cache content savings for task switching in a computer processor. An aspect includes determining a cache entry in a cache of the computer processor that is owned by the first thread, wherein the determination is made based on a hardware thread identifier (ID) of the first thread matching a hardware thread ID in the cache entry. Another aspect includes determining whether the determined cache entry is eligible for prefetching. Yet another aspect includes, based on determining that the determined cache entry is eligible for prefetching, setting a marker in the cache entry to active.

US Patent:

20160357676, Dec 8, 2016

Filed:

Jun 8, 2015

Appl. No.:

14/733168

Inventors:

- Armonk NY, US
David M. Daly - Croton on Hudson NY, US
Brian R. Prasky - Campball Hall NY, US
Vijayalakshmi Srinivasan - New York NY, US

International Classification:

G06F 12/08

Abstract:

Embodiments relate to a prefetch threshold for cache restoration. An aspect includes determining, based on a task switch from an outgoing task to a current task in a processor, a prefetch threshold for a next task, the prefetch threshold corresponding to an expected runtime of the current task and an amount of time required to prefetch data for the next task. Another aspect includes starting prefetching for the next task while the current task is executing based on the prefetch threshold.

US Patent:

20160320992, Nov 3, 2016

Filed:

Jul 8, 2016

Appl. No.:

15/205080

Inventors:

- Armonk NY, US
David M. Daly - Croton-on-Hudson NY, US
Gary A. Tressler - Sandy Hook CT, US

International Classification:

G06F 3/06
G06F 11/20

Abstract:

An SSD has a plurality of dies, with each die having a storage capacity. The storage capacity of each die is divided into a primary capacity and a spare capacity. A primary die has a maximum primary capacity, and a sum of the spare capacities of the remaining dies is greater than the maximum primary capacity. Data stored on the SSD is distributed among the primary capacities of the dies. When a failure of a first die is detected, data stored on the failed first die is migrated to the spare capacity of at least one of the remaining dies.

US Patent:

20160321180, Nov 3, 2016

Filed:

Jun 19, 2015

Appl. No.:

14/744354

Inventors:

- Armonk NY, US
David M. Daly - Croton on Hudson NY, US

International Classification:

G06F 12/08
G06F 12/12

Abstract:

A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the processor determines whether a memory region being accessed is marked as directory-based. Responsive to the given processor determining the memory region is marked as directory-based, the given processor accesses a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol. The given processor forwards the memory access request to the home chip to perform the memory access.

US Patent:

20160321191, Nov 3, 2016

Filed:

Apr 30, 2015

Appl. No.:

14/700526

Inventors:

- Armonk NY, US
David M. Daly - Croton on Hudson NY, US

International Classification:

G06F 12/12
G06F 12/08

Abstract:

A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the processor determines whether a memory region being accessed is marked as directory-based. Responsive to the given processor determining the memory region is marked as directory-based, the given processor accesses a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol. The given processor forwards the memory access request to the home chip to perform the memory access.