David G Daniel

US Patent:

6354908, Mar 12, 2002

Filed:

Jan 4, 2001

Appl. No.:

09/754429

Inventors:

Derryl D. J. Allman - Colorado Springs CO
David W. Daniel - Divide CO
John W. Gregory - Colorado Springs CO

Assignee:

LSI Logic Corp. - Milpitas CA

International Classification:

B24B 4900

US Classification:

451 6, 451 41

Abstract:

A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

US Patent:

6355532, Mar 12, 2002

Filed:

Oct 6, 1999

Appl. No.:

09/413667

Inventors:

John J. Seliskar - Northglenn CO
Verne Hornback - Troutdale OR
David Daniel - Vancouver WA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21336

US Classification:

438283, 438213, 438589, 438157

Abstract:

A short vertical channel, dual-gate, CMOS FET is fabricated by forming a plurality of channel segments in a starting material that extend longitudinally between source and drain areas. The channel segments are laterally separated from one another by spaces and are preferably formed from pillars of starting material located between the spaces. The pillars are laterally oxidized and the oxidation is removed to reduce the width of the pillars and form the channel segments. A gate structure is formed in the spaces between the channel segments. The width of each pillar is defined by conventional, contemporaneous photolithographic exposure and etching, but the width of each channel segment is substantially less than the width of the etch resistant barrier created photolithographically. The relatively narrow channel widths allow fully-depleted and fully-inverted conductivity characteristics which enhance the conductivity characteristics of the FET despite its reduced size, without silicon on insulator (SOI) constructions or epitaxial substrates.

US Patent:

6366422, Apr 2, 2002

Filed:

Apr 1, 1999

Appl. No.:

09/283170

Inventors:

David B. Daniel - Longmont CO
Fred Eifert - Eaton CO
Douglas Christian Hansen - Boulder CO
David Lawson - Arvada CO
Thai Nguyen - Thornton CO

Assignee:

Storage Technology Corporation - Louisville CO

International Classification:

G11B 500

US Classification:

360 76

Abstract:

It is difficult to read data from curved helical data tracks in a helical scan tape drive. Curved helical tracks can be caused by improper tape tension, tape damage, tape path misalignment, tape head offset between different head systems, and debris. The present invention solves the problem of recovering data from curved helical tracks by providing a table of different curve offset signals. Each curve offset signal represents a curve track profile of a typical curved track. The position of the helical read head reading a curved data track is controlled as a function of one of the curve offset signals such that the read head is positioned properly with respect to the helical data track to provide a proper read back signal. The curve offset signals are selected one at a time to control the position of the helical read head until the helical read head provides a proper read back signal.

US Patent:

6372520, Apr 16, 2002

Filed:

Jul 10, 1998

Appl. No.:

09/113594

Inventors:

George H. Maggard - Colorado Springs CO
David W. Daniel - Divide CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2100

US Classification:

438 4, 438308, 438378, 438795

Abstract:

A method and apparatus for repairing and improving the endurance characteristics of process damaged oxide film formed in a semiconductor device involving sonic annealing by vibrating or oscillating a wafer at a predetermined frequency, wave amplitude, and duration. A signal from a frequency generator is amplified by a voltage amplifier and then sent to a speaker or other acoustic device for the production of vibrating acoustical wave energy. This acoustical wave energy is then directed at a submicron device wafer during a specified time period in order to anneal the gate oxide and, thereby, improve the characteristics of the oxide film.

US Patent:

6565029, May 20, 2003

Filed:

Jun 20, 2001

Appl. No.:

09/885660

Inventors:

James Zweighaft - Boulder CO
David B. Daniel - Longmont CO

Assignee:

Quantum Corp. - Milpitas CA

International Classification:

G11B 1546

US Classification:

2423344, 2425342, 2425632, 360 71

Abstract:

A method for detecting slippage in a tape path, and re-calibrating a sensing assembly in a tape storage device to account for the slippage. The method includes sensing a position of one of a supply reel and a take-up reel. In response to sensing the position of the supply reel or take-up reel, sensing a position of a guide roller. The position of the guide roller corresponds to the position of the guide roller when the position of the supply reel or the take-up reel is sensed. In response to sensing the position of the guide roller, the tape media is wound through the tape path between the supply reel and the take-up reel. In response to winding the tape media through the tape path, a second position of the one of the supply reel and the take-up reel is sensed. In response to sensing the second position of the one of the supply reel and the take-up reel, a second position of the guide roller is sensed. The second position of the guide roller corresponds to the position of the guide roller when the second position of the one of the supply reel or the take-up reel is sensed.

US Patent:

6568618, May 27, 2003

Filed:

May 23, 2000

Appl. No.:

09/575977

Inventors:

William J. Vanderheyden - Loveland CO
Kevin S. Fletcher - Boulder CO
Michael J. OKeeffe - Boulder CO
David B. Daniel - Longmont CO

Assignee:

Quantum Corporation - Milpitas CA

International Classification:

G11B 1566

US Classification:

2423327, 2423328, 360 93

Abstract:

The half-inch tape drive comprises a novel takeup reel, tape deck, PC board packaging, loading mechanism, and housing. The takeup reel comprises a pair of segmented flanges that define a first and second tape containment section. The tape deck is approximately half the height of a conventional tape deck and includes reinforcing ribs to provide structural rigidity and maintain alignment of the moving components of the tape drive during operation. The loading mechanism comprises a horizontally mounted load motor that employs a worm gear to engage a simplified gear train. The printed circuit board is segmented into multiple sections that are mounted in various locations on the tape drive to maximize spatial efficiencies and reduce the overall height of the tape drive. The tape drive housing provides a protective exterior for the tape drive components and provides the structure for mounting the present tape drive in a single drive bay of a computer housing.

US Patent:

60966254, Aug 1, 2000

Filed:

Oct 20, 1997

Appl. No.:

8/954006

Inventors:

David W. Daniel - Divide CO
Theodore C. Moore - Woodland Park CO
Crystal J. Hass - Colorado Springs CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21322

US Classification:

438473

Abstract:

The present invention provides a method for manufacturing a semiconductor device on a substrate. The process involves denuding the substrate by heating to create a denuded zone within the substrate. A screen oxide layer is formed prior to implanting ions into the substrate. This oxide layer remains during the implantation step. The screen oxide layer is removed when forming gates for the semiconductor device.

US Patent:

59665998, Oct 12, 1999

Filed:

May 21, 1996

Appl. No.:

8/651018

Inventors:

John D. Walker - Colorado Springs CO
David W. Daniel - Divide CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 218238

US Classification:

438228

Abstract:

A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide layer. Field oxide regions are formed over regions other than the defined active regions. These field oxide regions are located between the active regions. The remaining portions of the silicon nitride layer and the thin oxide layer are removed and a sacrificial oxide layer is then grown on the surfaces of the active regions. A first mask, a N-well mask, is formed for implanting N-type dopants. A buried layer implanted using P-type dopants with the first mask in place. Thereafter, the N-well regions are implanted. The first mask is removed and a second mask is formed to define regions for implanting P-well regions using P-type dopants.

Address:

9993 Salida St, Commerce City, CO 80022

VIN:

1HGCM56827A078894

Make:

HONDA

Model:

ACCORD

Year:

2007