David Davidian

US Patent:

54386462, Aug 1, 1995

Filed:

Aug 19, 1992

Appl. No.:

7/932827

Inventors:

David Davidian - Cambridge MA

Assignee:

NEC Electronics, Inc. - Mountain View CA

International Classification:

G06F 1518

US Classification:

395 26

Abstract:

A Forward Feed Neural Network is disclosed using data flow techniques on a data flow microprocessor. As a result of this invention, a neural network is provided that has the capacity of "learning" to distinguish among patterns of data which may differ recognizably from idealized cases, and is able to perform pattern recognition faster while utilizing less memory and fewer clock cycles than neural networks implemented on sequential processors. This implementation is simpler and faster because of an inherent similarity between the flow of information in the brain and in data flow architecture.

US Patent:

52609090, Nov 9, 1993

Filed:

Nov 18, 1991

Appl. No.:

7/793979

Inventors:

David Davidian - Cambridge MA

Assignee:

NEC Electronics Incorporated - Mountain View CA

International Classification:

G11C 804

US Classification:

365233

Abstract:

A memory circuit is provided with a phase locked serial input port that is adapted to receive unsynchronized raw serial data. The memory eliminates complex serial input timing problems associated with conventional video RAM, and allows direct connection to high speed external storage devices and communication devices. The memory circuit includes a memory array having an input port and an output port, a serial sequential circuit coupled to the memory array for loading data into the memory array, and a phase locked loop circuit for receiving raw serial data. The phase locked loop circuit is coupled to the serial sequential circuit for providing a synchronized data signal and a clock signal to the serial sequential circuit.

US Patent:

52970736, Mar 22, 1994

Filed:

Aug 19, 1992

Appl. No.:

7/932393

Inventors:

David Davidian - Cambridge MA

Assignee:

NEC Electronics, Inc. - Mountain View CA

International Classification:

G06F 752

US Classification:

364766

Abstract:

In accordance with the present invention, a method of performing arithmetic division on a data flow machine is disclosed which resolves some of the inefficiencies associated with the conventional subtract until carry method. This method eliminates many of the numerous subtraction operations characterizing the conventional method by performing trial multiplications in the same way long hand division is performed. Furthermore, the method is implemented using data flow techniques to enhance the speed of the division by performing functions in parallel with a minimal memory requirement. As a result of this invention, integer division is performed using fewer clock cycles than a conventional Von Neuman implementation.