David L Dooley

US Patent:

6477174, Nov 5, 2002

Filed:

Jan 22, 1998

Appl. No.:

09/010891

Inventors:

David Dooley - San Jose CA
David A. Hughes - Mountain View CA

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 1242

US Classification:

370416

Abstract:

A switch node includes arbiter logic configured to gather global information regarding switching requests within the switch node and to control switching of one or more packets through the switch node. The arbiter logic may include a bus snooping interface configured to detect the switching requests within the switch node. The bus snooping interface includes a plurality of switching request destination registers configured to store switching request destination information from the detected switching requests. In addition, the arbiter logic includes a packet switching request array configured to transmit a next switching request within the switch node according to prior switching request destination information stored in the switching request destination registers. The switching of the one or more packets may be through a cross-point switch matrix in the switch node.

US Patent:

6959002, Oct 25, 2005

Filed:

Jul 18, 2001

Appl. No.:

09/908614

Inventors:

John M. Wynne - Sunnyvale CA, US
David L. Dooley - San Jose CA, US
Robert J. Divivier - San Jose CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

H04L012/28
H04L012/54
H04L012/56

US Classification:

370412, 370389, 370429

Abstract:

A traffic manager for a network switch input or output port stores incoming cells in a cell memory and later sends each cell out of its cell memory toward one of a set of forwarding resources such as, for example, another switch port or an output bus. Data in each cell references the particular forwarding resource to receive the cell. Each cell is assigned to one of several flow queues such that all cells assigned to the same flow queue are to be sent to the same forwarding resource. The traffic manager maintains a separate virtual output queue (VOQ) associated with each forwarding resource and periodically loads a flow queue (FQ) number identifying each flow queue into the VOQ associated with the forwarding resource that is to receive the cells assigned to that FQ. The traffic manager also periodically shifts an FQ ID out of each non-empty VOQ and forwards the longest-stored cell assigned to that FQ from the cell memory toward its intended forwarding resource. The traffic manager separately determines the rates at which it loads FQ IDs into VOQs and the rates at which it shifts FQ IDs out of each non-empty VOQ.

US Patent:

7058057, Jun 6, 2006

Filed:

May 1, 2001

Appl. No.:

09/847077

Inventors:

David L. Dooley - San Jose CA, US
Robert J. Divivier - San Jose CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

H04L 12/28

US Classification:

370394, 3703957, 370428

Abstract:

An input or output switch port for a network switch converts each incoming packet into a cell sequence stores each cell in a cell memory. The switch port includes a traffic manager for queuing cells for departure from the cell memory and then signaling the cell memory to read out and forward cells in the order they are queued. The traffic manager selectively queues cells for departure on either a cell-by-cell or sequence-by-sequence basis. When cells are queued for departure on a cell-by-cell basis, cells of two or more sequences may be alternately read out and forwarded from the cell memory. Thus cells of different sequences may be interleaved with one another as they depart the cell memory. When a cell sequence is queued on a sequence-by-sequence basis all of its cells are read out of the cell memory and forwarded as a contiguous sequence and are not interleaved with cells of other sequences of the same departure queue. Each packet includes a flow identification number (FIN) value and the traffic manager determines from the packet's FIN whether to queue cell sequences derived from the packet on a cell-by-cell or sequence-by-sequence basis.

US Patent:

7072350, Jul 4, 2006

Filed:

Sep 17, 2002

Appl. No.:

10/245932

Inventors:

David Dooley - San Jose CA, US
David A. Hughes - Mountain View CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 12/28

US Classification:

370416

Abstract:

A switch node includes arbiter logic configured to gather global information regarding switching requests within the switch node and to control switching of one or more packets through the switch node. The arbiter logic may include a bus snooping interface configured to detect the switching requests within the switch node. The bus snooping interface includes a plurality of switching request destination registers configured to store switching request destination information from the detected switching requests. In addition, the arbiter logic includes a packet switching request array configured to transmit a next switching request within the switch node according to prior switching request destination information stored in the switching request destination registers. The switching of the one or more packets may be through a cross-point switch matrix in the switch node.

US Patent:

7203170, Apr 10, 2007

Filed:

May 1, 2001

Appl. No.:

09/847076

Inventors:

David L. Dooley - San Jose CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

G01R 31/08
H04L 12/28

US Classification:

370235, 3703957, 370412, 370470

Abstract:

A network switch port receives, stores and then forwards incoming cells. The network switch assigns each incoming cell to one of a set of flow queues, each of which is allotted a portion of space in a cell memory. The switch port periodically computes a average of the number of cells assigned to each flow queue stored in the cell memory during a preceding period, and assigns a discard weight to each incoming cell that is a function of the amount by which the average for the cell's assigned flow queue exceeds a threshold level. The switch port randomly discards incoming cells assigned to the flow queue with a probability that increases with the incoming cells' assigned weights. The switch port stores incoming cells that are not randomly discarded in the cell memory and later forewords them from the cell memory.

US Patent:

7809871, Oct 5, 2010

Filed:

Dec 7, 2006

Appl. No.:

11/608236

Inventors:

Lambert Fong - San Ramon CA, US
David L. Dooley - San Jose CA, US

Assignee:

Integrated Device Technology Inc. - San Jose CA

International Classification:

G06F 13/00
G06F 13/36
G06F 15/16

US Classification:

710110, 710306, 709251

Abstract:

A common access ring (CAR) architecture that supports multiple masters and slaves is provided. One or more masters may make a request on the ring at the same time, such that multiple transactions are simultaneously pending. Moreover, multiple masters may simultaneously make a request to the same slave. However, each master cannot make more than one request at a time, and must wait until a current request is completed before making another request. The ring architecture ensures that no more than one request arrives at a slave at any given time. If a request arrives while a slave is processing a previous request, the arriving request is not serviced, and the master that originated the arriving request is asked to retry the request at a later time. Atomic shadow-write operations are supported by including all shadow registers in a dedicated sub-ring of the CAR architecture.

US Patent:

7814248, Oct 12, 2010

Filed:

Dec 7, 2006

Appl. No.:

11/608239

Inventors:

Lambert Fong - San Ramon CA, US
David L. Dooley - San Jose CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

G06F 13/00
G06F 13/36
G06F 15/16

US Classification:

710110, 710306, 709251

Abstract:

A common access ring (CAR) network includes a main ring and one or more sub-rings. The main ring includes one or more masters, one or more slaves, and one or more bridges. Each sub-ring is coupled to the main ring through a corresponding bridge. Each node of the CAR network is assigned a unique identifier, thereby implementing a global flat address space. One or more masters may issue requests on the CAR network, such that multiple transactions are simultaneously pending. Multiple masters may simultaneously issue requests to the same slave. However, each master cannot make more than one request at a time, and must wait until a current request is completed before making another request. The ring architecture ensures that no more than one request arrives at a slave at any given time. Requests received by busy slaves are returned to the originating masters, and may be subsequently re-sent.

US Patent:

53677013, Nov 22, 1994

Filed:

Dec 21, 1992

Appl. No.:

7/994122

Inventors:

Mark von Gnechten - Fremont CA
Brian T. Chase - San Jose CA
Richard J. Tobias - Santa Rosa CA
David Dooley - San Jose CA

Assignee:

Amdahl Corporation - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

395800

Abstract:

A partitionable computing system includes main storage units on respective sides of the complex which can be fully controlled and accessible from either side. The system includes a dual port main storage unit design, and a system controller design capable of driving plural main storage unit interfaces. With this configuration, one system controller and the processors attached to that system controller can be taken offline and partitioned off to perform maintenance while all of the physical main storage units remain accessible to the processors on the surviving side of the complex. The operating system sees no loss available memory and the time to perform the maintenance activity is significantly reduced.