David O Dougherty

US Patent:

7042103, May 9, 2006

Filed:

Dec 30, 2002

Appl. No.:

10/334042

Inventors:

Brian W. Condie - Mesa AZ, US
David J. Dougherty - Tempe AZ, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 23/52

US Classification:

257782, 257778, 257779, 257663, 257676, 257674, 257783, 257773

Abstract:

A semiconductor device () is provided which comprises a substrate and a die () having a first surface which is attached to the substrate by way of a die attach material. At least a portion () of the perimeter of the die is resistant to wetting by the die attach material, either through treatment with a dewetting agent or by selective removal of the backside metallization. It is found that this construction allows the surface area of the die to be increased without increasing the incidence of cracking and chipping along the sawn edges of the die.

US Patent:

7332414, Feb 19, 2008

Filed:

Jun 22, 2005

Appl. No.:

11/159553

Inventors:

Brian W. Condie - Mesa AZ, US
David J. Dougherty - Tempe AZ, US
Mahesh K. Shah - Scottsdale AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

438460, 438462, 438464, 257E21001

Abstract:

A method is provided for manufacturing a semiconductor device from a substrate () having an active surface () and a non-active surface (). The method comprises depositing a backing material () onto the non-active surface of the substrate () in a pattern (), the pattern () having at least a first die section (), a second die section () adjacent the first die section (), and a strip () connecting the first die section () and the second die section (), removing material from portions of the non-active surface of the substrate () on which the backing material () is not deposited to thereby partially separate the substrate () into a first die () and a second die () connected to one another by the strip () of the deposited backing material, and breaking the strip connector () to separate the first die () from the second die ().

US Patent:

7423804, Sep 9, 2008

Filed:

Oct 4, 2005

Appl. No.:

11/243021

Inventors:

Daniel Al-Salameh - Marlboro NJ, US
David J. Dougherty - Mountain View CA, US

Assignee:

JDS Uniphase Corporation - Milpitas CA

International Classification:

H01S 3/00

US Classification:

359337, 3593371

Abstract:

A method and apparatus for monitoring spectral tilt uses an arrayed waveguide grating (AWG) to separate a multiplexed optical signal having a plurality of wavelength channels into a plurality of sub-bands, where each sub-band spans a different wavelength range and includes more than one wavelength channel. A photodetector array is provided to measure the optical power in each of the sub-bands, while control electronics calculate spectral tilt of the multiplexed optical signal using the measured optical power in each of the sub-bands. The spectral tilt monitor in accordance with the instant invention provides spectral resolution, increased monitoring speeds, and decreased manufacturing costs.

US Patent:

7768697, Aug 3, 2010

Filed:

Aug 5, 2008

Appl. No.:

12/185893

Inventors:

Daniel Al-Salameh - Marlboro NJ, US
David J. Dougherty - Mountain View CA, US

Assignee:

JDS Uniphase Corporation - Milpitas CA

International Classification:

H01S 3/00

US Classification:

359333, 385 37, 385 48

Abstract:

A method and apparatus for monitoring spectral tilt uses an arrayed waveguide grating (AWG) to separate a multiplexed optical signal having a plurality of wavelength channels into a plurality of sub-bands, where each sub-band spans a different wavelength range and includes more than one wavelength channel. A photodetector array is provided to measure the optical power in each of the sub-bands, while control electronics calculate spectral tilt of the multiplexed optical signal using the measured optical power in each of the sub-bands. The spectral tilt monitor in accordance with the instant invention provides spectral resolution, increased monitoring speeds, and decreased manufacturing costs.

US Patent:

7989951, Aug 2, 2011

Filed:

Feb 12, 2010

Appl. No.:

12/704941

Inventors:

Betty H. Yeung - Chandler AZ, US
David J. Dougherty - Tempe AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/12

US Classification:

257732, 257E23026, 257710, 257728, 438122, 174521

Abstract:

An embodiment of a die assembly includes a flange, lip walls, and leads for electrical contact with one or more die mounted on the flange. The flange has first and second opposed flange surfaces and flange sidewalls extending between the surfaces. The lip walls have first and second opposed lip surfaces and lip sidewalls extending between the first and second lip surfaces. The lip sidewalls are positioned adjacent to the flange sidewalls. The leads, which have inboard end portions and outboard end portions, are configured to preserve a seating plane. The seating plane is spaced apart from a plane of the second flange surface. The inboard end portions of the leads are embedded in the lip walls, and extend from the seating plane upward through the lip walls toward the first lip surfaces. The outboard end portions are aligned substantially within the seating plane.

US Patent:

20070175660, Aug 2, 2007

Filed:

Jan 27, 2006

Appl. No.:

11/341991

Inventors:

Betty Yeung - Chandler AZ, US
David Dougherty - Tempe AZ, US

International Classification:

H01L 23/34

US Classification:

174521000, 257202000

Abstract:

A flange and packaging assembly characterized by a structural lip configured to impart resistance to thermal-induced deformation (i.e. “stiffness”) to the flange during elevated temperature die attachment processes. The stiffness is achieved through appropriate configuration of the lip (height, width and shape) and is sufficient to at least partially counteract the stresses generated from coefficient of thermal expansion differentials between the flange and a die attached to it. The lip may be molded or otherwise formed with the flange as a unitary lip-stiffened flange, or may be a separate structure that is affixed to the flange. The flange has a lip-stiffened region for die attachment. This region may be raised above the first surface of the substrate base for enhanced stiffening, and may be in the form of a single pedestal supporting a single or multiple die, or may be a series of raised pedestals, each supporting one or more die. The leads may be embedded in a polymetric material that is attached to the flange that is of sufficient thickess to provide the required stiffness. The embedded leads may be shaped and formed so that the desired seating plane height is achieved. The lead form placement can be either on the interior or exterior of the embedded polymetric material. The polymetric material can be supported along the edge of the flange or be seated on a part of an extrusion from the flange.

US Patent:

20140022020, Jan 23, 2014

Filed:

Jul 20, 2012

Appl. No.:

13/554034

Inventors:

Peter H. Aaen - Phoenix AZ, US
David J. Dougherty - Tempe AZ, US
Manuel F. Romero - Chandler AZ, US
Lakshminarayan Viswanathan - Phoenix AZ, US

International Classification:

H01L 23/60
H03F 3/68

US Classification:

330295, 257659, 257E23114

Abstract:

A single semiconductor device package that reduces electromagnetic coupling between elements of a semiconductor device embodied within the package is provided. For a dual-path amplifier, such as a Doherty power amplifier, an isolation feature that separates carrier amplifier elements from peaking amplifier elements is included within the semiconductor device package. The isolation feature can take the form of a structure that is constructed of a conductive material coupled to ground and which separates the elements of the amplifier. The isolation feature can be included in a variety of semiconductor packages, including air cavity packages and overmolded packages. Through the use of the isolation feature provided by embodiments of the present invention a significant improvement in signal isolation between amplifier elements is realized, thereby improving performance of the dual-path amplifier.

US Patent:

56599501, Aug 26, 1997

Filed:

Mar 23, 1995

Appl. No.:

8/409130

Inventors:

Victor J. Adams - Tempe AZ
David J. Dougherty - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01R 4300

US Classification:

29827

Abstract:

A method of forming a package assembly (10) including a package (12) that encapsulates an electronic die. A leadframe (30) has edge rails (32), and the die is disposed on the leadframe. The package is formed around the die to encapsulate it, and the leadframe is trimmed to provide a plurality of leads (14) protruding from a first side of the package. This trimming also provides a support (16) connected to a second side of the package. The support is bent to be substantially orthogonal to the common plane containing the leads. A mounting tip (26) on the support is thus disposed outside of the common plane. This support improves the rigidity and natural bending frequency of the package assembly.