David Howard Douglas

US Patent:

7763396, Jul 27, 2010

Filed:

Feb 16, 2006

Appl. No.:

11/355757

Inventors:

David C. Douglas - Palo Alto CA, US
Ronald Ho - Mountain View CA, US
Robert J. Drost - Los Altos CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G03F 9/00

US Classification:

430 5, 430311

Abstract:

A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.

US Patent:

7949436, May 24, 2011

Filed:

May 19, 2006

Appl. No.:

11/437456

Inventors:

Robert J. Drost - Los Altos CA, US
Ronald Ho - Mountain View CA, US
David C. Douglas - Palo Alto CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G05D 1/02

US Classification:

700302, 700121

Abstract:

One embodiment of the present invention provides a system that automatically detects and corrects a misalignment of a semiconductor chip. During operation, the system uses a position-detection mechanism integrated with the chip to determine the misalignment of the chip from a desired alignment for the chip. Next, the system uses an actuation mechanism integrated with the chip to automatically correct the misalignment, thereby improving performance and reliability of the chip.

US Patent:

8283766, Oct 9, 2012

Filed:

Sep 2, 2010

Appl. No.:

12/874446

Inventors:

John A. Harada - Mountain View CA, US
David C. Douglas - Palo Alto CA, US
Robert J. Drost - Los Altos CA, US

Assignee:

Oracle America, Inc - Redwood Shores CA

International Classification:

H01L 23/52
H01L 23/48
H01L 23/495
H01L 23/02

US Classification:

257686, 257E23141, 257723, 257777, 257685, 257728, 257737, 257738, 257778, 257773, 257774, 257691, 257E23169, 257692, 257784, 257786

Abstract:

A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

US Patent:

8290319, Oct 16, 2012

Filed:

Aug 25, 2010

Appl. No.:

12/868577

Inventors:

John A. Harada - Mountain View CA, US
David C. Douglas - Palo Alto CA, US
Robert J. Drost - Los Altos CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G02B 6/43

US Classification:

385 39, 385 14, 385 89, 439577

Abstract:

A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a stepped terrace. A high-bandwidth ramp component, which is positioned approximately parallel to the stepped terrace, is mechanically coupled to the semiconductor dies. Furthermore, the ramp component includes an optical waveguide that conveys the optical signal, and an optical coupling component that optically couples the optical signal to one of the semiconductor dies, thereby facilitating high-bandwidth communication of the optical signal between the semiconductor die and the ramp component.

US Patent:

8373280, Feb 12, 2013

Filed:

Sep 1, 2010

Appl. No.:

12/873945

Inventors:

John A. Harada - Mountain View CA, US
Robert J. Drost - Los Altos CA, US
David C. Douglas - Palo Alto CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H01L 23/498
H01L 21/50

US Classification:

257777, 257E23069, 257E21499, 257773, 257686, 257723, 257724, 257728, 257778, 257737, 257738

Abstract:

An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terraced at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a housing having another stepped terrace. This other stepped terrace may include a sequence of steps in the vertical direction, which are offset from each other in the horizontal direction. Furthermore, the housing may be configured to mate with the set of semiconductor dies such that the set of semiconductor dies are arranged in the stack in the vertical direction. For example, the other stepped terrace may approximately be a mirror image of the stepped terrace.

US Patent:

8476749, Jul 2, 2013

Filed:

Jul 22, 2009

Appl. No.:

12/507349

Inventors:

Robert J. Drost - Los Altos CA, US
James G. Mitchell - Palo Alto CA, US
David C. Douglas - Palo Alto CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H01L 23/02

US Classification:

257686, 257685, 257777, 257723, 257691, 257784

Abstract:

A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.

US Patent:

20100244288, Sep 30, 2010

Filed:

Jun 11, 2010

Appl. No.:

12/813808

Inventors:

David C. Douglas - Palo Alto CA, US
Ronald Ho - Mountain View CA, US
Robert J. Drost - Los Altos CA, US

Assignee:

ORACLE INTERNATIONAL CORPORATION - Redwood City CA

International Classification:

H01L 23/544
G03B 27/52

US Classification:

257797, 355 55, 257E23179

Abstract:

A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.

US Patent:

20150068776, Mar 12, 2015

Filed:

Apr 2, 2014

Appl. No.:

13/999917

Inventors:

David C. Douglas - Palo Alto CA, US

International Classification:

A62C 3/02

US Classification:

169 48

Abstract:

A fire-protection mechanism is described. The fire-protection mechanism includes multiple, overlapping cavities that can be filled with water (and, more generally, a fluid). When the fire-protection mechanism is deployed over an object, such as a building, and the cavities are filled with water, the fire-protection mechanism reduces the likelihood that the object is damaged by the heat associated with a fire proximate to the object, such as a wild fire. In particular, the heat capacity and latent heat of the water significantly increase the thermal time constant of the object, thereby reducing the likelihood of combustion. The fire-protection mechanism may include a reflective coating to redirect infrared radiation away from the object to provide further protection. In addition, the water in the cavities may be refilled, as needed, by directing a stream of water onto the fire-protection mechanism and/or through an internal channel in the fire-protection mechanism.