David J Duarte

US Patent:

8314725, Nov 20, 2012

Filed:

Sep 15, 2010

Appl. No.:

12/883125

Inventors:

Paola Zepeda - Chandler AZ, US
David E. Duarte - Portland OR, US
Gregory F. Taylor - Portland OR, US
Atul Maheshwari - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 1/10

US Classification:

341120, 341118, 341119, 341121, 341155

Abstract:

In one embodiment, an analog-to-digital conversion in an integrated circuit is evaluated by an on-die testing circuit. For example, the on-die test circuit can characterize one or both of the linearity and monotonicity of the digital-to-analog conversion. The value of a conversion output for a digital input code may be compared to the value of a prior conversion output of a prior step to provide digital difference values for each step of a sweep of digital input codes. Digital difference values may be compared to one or more predetermined limits to provide one or more pass/fail tests on-board the die. Other embodiments are described and claimed.