David M Durham

US Patent:

6601082, Jul 29, 2003

Filed:

Jul 30, 1999

Appl. No.:

09/365101

Inventors:

David M. Durham - Hillsboro OR
Russell J. Fenger - Beaverton OR
Rajendra S. Yavatkar - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 900

US Classification:

709100, 709223

Abstract:

A system and method for managing a network using a policy tree which includes a plurality of levels (e. g. , two levels, five levels, etc. ) is described. When the network receives a request to provide an action to a particular source, the network determines if the action is available as a function of at least one level of the plurality of levels. If the action is available, the network determines if the particular source is authorized to be provided with the action as a function of at least one rule of at least one further level of the plurality of levels. If the particular source is authorized, the network provides the action to the particular source.

US Patent:

6704319, Mar 9, 2004

Filed:

Dec 21, 1998

Appl. No.:

09/217761

Inventors:

David M. Durham - Hillsboro OR
Russell J. Fenger - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 1228

US Classification:

370408, 370256, 709252

Abstract:

A network route tracing system traces a path through a network and identifies network components and communications links affected by the path. According to one embodiment of the present invention, a route is traced between two hosts in a network. The network is represented as a logical tree having a plurality of nodes. Each one of the nodes corresponds to a component in the network and each non-root node has a parent node. Two nodes are identified in the logical tree. A first node corresponds to a first host and a second node corresponding to a second host. If one of the two nodes exists at a lower level of the logical tree, then a first path is traced from the first node at the lower level to the parent node at a higher level until the parent node is at a same level of the logical tree as the second node. The first path is further traced up the logical tree from the parent node and a second path is traced up the logical tree from the second node until the first path and the second path meet at a same node.

US Patent:

6751659, Jun 15, 2004

Filed:

Mar 31, 2000

Appl. No.:

09/541146

Inventors:

Russell J. Fenger - Beaverton OR
David M. Durham - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15173

US Classification:

709223, 709224, 709222, 709221

Abstract:

Selecting a subset of a hierarchical data structure based on a correspondence of the subset with a target in a communication network, and sending the subset of the hierarchical data structure to the target.

US Patent:

6973488, Dec 6, 2005

Filed:

Mar 31, 2000

Appl. No.:

09/539916

Inventors:

Rajendra S. Yavatkar - Portland OR, US
David M. Durham - Hillsboro OR, US
Russell J. Fenger - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F015/16

US Classification:

709223, 709224, 709225

Abstract:

Policy information is distributed to remote network devices by mapping high-level policy information into low-level configuration information and distributing the low-level configuration information to the remote network devices.

US Patent:

7065598, Jun 20, 2006

Filed:

Dec 20, 2002

Appl. No.:

10/326740

Inventors:

Patrick L. Connor - Portland OR, US
Eric K. Mann - Hillsboro OR, US
Hieu T. Tran - Portland OR, US
Priya Govindarajan - Hillsboro OR, US
John P. Jacobs - Beaverton OR, US
David M. Durham - Hillsboro OR, US
Gary D. Gumanow - Portland OR, US
Chun Yang Chiu - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/24

US Classification:

710260, 710266, 710261, 370463

Abstract:

Provided are a method, system and article of manufacture for adjusting interrupt levels. A current system interrupt rate at a computational device is determined, wherein the current system interrupt rate is a sum of interrupt rates from a plurality of interrupt generating agents. The current system interrupt rate is compared with at least one threshold interrupt rate associated with the computational device. Based on the comparison, an interrupt moderation level is adjusted at an interrupt generating agent of the plurality of interrupt generating agents.

US Patent:

7072958, Jul 4, 2006

Filed:

Jul 30, 2001

Appl. No.:

09/919059

Inventors:

Pankaj N. Parmar - Beaverton OR, US
David M. Durham - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/173

US Classification:

709223, 709220

Abstract:

A policy based network management (PBNM) system may identify one or more policies associated with a network component (e. g. , a network device, a device group, a device subgroup, a user, an application, an end-host, etc. ) by identifying one or more policies directly associated with the network component, generating a list of one or more groups to which the network component belongs, and identifying one or more policies associated with each of the groups in the generated list. An aggregated data set (e. g. , a hash table or a balanced tree) may be used to store network component identity elements, one or more pointers to a deployed policy tree, and one or more pointers to a network configuration tree. Each identity element in the data set identifies a network component and has an associated network configuration tree pointer and one or more associated deployed policy tree pointers.

US Patent:

7110540, Sep 19, 2006

Filed:

Apr 25, 2002

Appl. No.:

10/134066

Inventors:

Priya Rajagopal - Hillsboro OR, US
David M. Durham - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 9/00

US Classification:

380 44, 380 28, 380262, 380281, 713181, 707 3, 707 6, 707101

Abstract:

A hash table randomly populated with byte patterns is used in finding the byte patterns in a sequence of bytes. A hash function is applied to information associated with a substring of the sequence of bytes to generate a key value. The key value is compared to the keys of the hash table, and if a match is found, the information associated with the substring is compared to corresponding information associated with a substring of a byte pattern stored in the hash table. If a match is found, the substring of the sequence of bytes is compared to the substring of the byte pattern. If a match is found, the substring is compared to the byte pattern.

US Patent:

7194556, Mar 20, 2007

Filed:

Mar 30, 2001

Appl. No.:

09/823070

Inventors:

Priya Rajagopal - Hillsboro OR, US
David M. Durham - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/16

US Classification:

709248, 713375, 713400, 375354

Abstract:

A method and apparatus are provided that allow processing engines to be synchronized to each other with high accuracy. In one embodiment, the invention includes obtaining a processor tick counter value from a first processing engine, comparing the obtained processor tick counter value to a processor tick counter value from a second processing engine and determining a timing offset for synchronizing the first processing engine and the second processing engine using the comparison. The invention may further include obtaining a processor tick counter value by sending a request message from the second processing engine to the first processing engine, and receiving a reply from the first processing engine at the second processing engine. The processor tick counter value at the second processing engine can be determined by recording the time at which the request message is sent and by recording the time at which the reply is received. The invention can further include obtaining a processor frequency from the first processing engine, obtaining a processor frequency from the second processing engine and correcting the timing offset for any difference between the first processing engine frequency and the second processing engine frequency.