David Y Fang

US Patent:

20190384603, Dec 19, 2019

Filed:

Aug 30, 2019

Appl. No.:

16/557187

Inventors:

Jason Seung-Min Kim - San Jose CA, US
Nitin N. Garegrat - San Jose CA, US
Anitha Loke - Santa Clara CA, US
Nasima Parveen - San Jose CA, US
David Y. Fang - San Jose CA, US
Kursad Kiziloglu - Pleasanton CA, US
Dmitry Sergeyevich Lukiyanchenko - Beaverton OR, US
Fabrice Paillet - Portland OR, US
Andrew Yang - Cupertino CA, US

International Classification:

G06F 9/30

Abstract:

Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.