David E Farber

US Patent:

53534190, Oct 4, 1994

Filed:

Jan 9, 1992

Appl. No.:

7/819100

Inventors:

Joseph D. Touch - Willingboro NJ
David J. Farber - Landenberg PA

Assignee:

Trustees of the University of Pennsylvania - Philadelphia PA

International Classification:

G06F 900
G06F 930

US Classification:

395375

Abstract:

A computer architecture which significantly reduces latency in fetching instructions from main memory includes a code-pump located proximate to the memory and a filter cache located proximate to the processor. The code pump reduces latency in fetching instructions by predicting possible instruction streams that may be executed by the processor and passing instructions from all possible streams to the filter cache. The code pump fetches instructions from the memory and partially decodes the instructions to determine their types. Instruction types which may change the flow of the program such as subroutine calls and conditional branches, cause the code pump to concurrently supply instructions from all flow paths that can be predicted from these instructions. To keep track of the possible flow paths, the code pump maintains a data structure which is a combination of multiple stack entries (for call instructions) and tree entries (for branch instructions). The filter cache passes the addresses of fetched instructions back to the code pump.

US Patent:

53296230, Jul 12, 1994

Filed:

Nov 12, 1993

Appl. No.:

8/152085

Inventors:

Jonathan M. Smith - Philadelphia PA
C. Brendan S. Traw - Bensalem PA
David J. Farber - Landenberg PA

Assignee:

The Trustees of the University of Pennsylvania - Philadelphia PA

International Classification:

G06F 1502

US Classification:

395275

Abstract:

A host interface comprising a reassembler for reassembling and decrypting data that has been encrypted in accordance with a pre-defined key and segmented into a plurality of asynchronous transfer mode (ATM) cells. Each cell comprises a virtual channel identifier (VCI), a multiplexing identifier (MID) if the data is transmitted using the CCITT specified Class 4 connectionless transfer ATM adaptation layer (AAL), and a cell body. The reassembler comprises a cell manager for separating each cell body from that cell body's corresponding VCI and MID (if present), a linked list manager for managing and storing linked list data indicative of addresses at which the cell bodies are to be stored, a content addressable memory (CAM) for managing and storing the VCIs (and MIDs for connectionless data) and providing pointers into the linked list data, a lookup controller for writing the VCIs to the CAM, a reassembly buffer for storing the cell bodies, and a decryption device for decrypting the data and writing the decrypted data to the reassembly buffer. The major subsections operate concurrently to form an ATM cell-processing pipeline. The interface may also comprise a segmenter for encrypting data received from a host computer and segmenting the encrypted data into a plurality of ATM cells.