David P Farber

US Patent:

6780756, Aug 24, 2004

Filed:

Feb 28, 2003

Appl. No.:

10/375996

Inventors:

David G. Farber - Wylie TX
Ting Tsui - Plano TX
Robert Kraft - Plano TX
Craig Huffman - Krugerville TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 214763

US Classification:

438622, 438631, 438690, 438761

Abstract:

An embodiment of the invention is a metal layer of a back-end module where the height of the interconnects is greater than the height of the dielectric regions. Another embodiment of the invention is a method of fabricating a semiconductor wafer where the height of the interconnects is greater than the height of the dielectric regions.

US Patent:

7087518, Aug 8, 2006

Filed:

May 15, 2003

Appl. No.:

10/438566

Inventors:

David Gerald Farber - Wylie TX, US
William Wesley Dostalik - Plano TX, US
Robert Kraft - Plano TX, US
Andrew J. McKerrow - Dallas TX, US
Kenneth Joseph Newton - Mckinney TX, US
Ting Tsui - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/322

US Classification:

438633, 438622, 438471

Abstract:

One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

US Patent:

7112288, Sep 26, 2006

Filed:

Aug 13, 2002

Appl. No.:

10/218046

Inventors:

Fred Y. Clark - Rowlett TX, US
Andrew L. Vance - Rowlett TX, US
David G. Farber - Wylie TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/00

US Classification:

216 59, 216 60, 216 62, 216 72, 438712

Abstract:

Methods are provided for delineating different layers and interfaces for inspection of a semiconductor wafer, wherein a sectioned portion of a wafer is subjected to a reactive ion etch process before inspection using a scanning electron microscope.

US Patent:

7687407, Mar 30, 2010

Filed:

Mar 2, 2005

Appl. No.:

11/070593

Inventors:

David G. Farber - Wylie TX, US
Robert Kraft - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/302

US Classification:

438734, 216 39, 257288

Abstract:

The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion () of a substrate () to a first etch process, the first etch process designed to etch at a first entry angle (θ), and subjecting a second portion () of the substrate () to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (θ).

US Patent:

7741663, Jun 22, 2010

Filed:

Oct 24, 2008

Appl. No.:

12/258188

Inventors:

Fred Hause - Austin TX, US
Anthony C. Mowry - Buda TX, US
David G. Farber - Austin TX, US
Markus E. Lenski - Dresden, DE

Assignee:

Globalfoundries Inc. - Grand Cayman

International Classification:

H01L 29/772
H01L 21/336

US Classification:

257288, 257900, 257E21409, 257E29255, 438300, 438303, 438421, 438422, 438595

Abstract:

Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.

US Patent:

7745337, Jun 29, 2010

Filed:

May 19, 2008

Appl. No.:

12/122840

Inventors:

David G. Farber - Austin TX, US
Fred Hause - Austin TX, US
Markus Lenski - Dresden, DE
Anthony C. Mowry - Buda TX, US

Assignee:

Globalfoundries Inc. - Grand Cayman

International Classification:

H01L 21/311

US Classification:

438696, 438704, 257E21224, 257E21226, 257E21256

Abstract:

A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.

US Patent:

8064197, Nov 22, 2011

Filed:

May 22, 2009

Appl. No.:

12/470956

Inventors:

Anthony C. Mowry - Buda TX, US
David G. Farber - Austin TX, US
Michael J. Austin - Austin TX, US
John E. Moore - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H05K 7/20
G06F 1/00

US Classification:

36167953, 36167946, 361688, 361689, 361699, 361719, 713300, 713320, 713322, 700299, 700300, 257714, 165 803, 165 804, 165 805, 16510433, 702130, 62 32, 622592

Abstract:

A multi-core microprocessor provides an indication of the power management state of each of the cores on output terminals. Cooling of the cores is adjusted responsive to the indication of the power management state of the respective cores with additional cooling being provided to those cores in a more active state and less cooling provided to those cores in a less active state.

US Patent:

8507386, Aug 13, 2013

Filed:

Sep 13, 2010

Appl. No.:

12/880959

Inventors:

David Gerald Farber - Plano TX, US
Tom Lii - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/302

US Classification:

438719, 438727, 438739

Abstract:

A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.