David M Farber

US Patent:

6780756, Aug 24, 2004

Filed:

Feb 28, 2003

Appl. No.:

10/375996

Inventors:

David G. Farber - Wylie TX
Ting Tsui - Plano TX
Robert Kraft - Plano TX
Craig Huffman - Krugerville TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 214763

US Classification:

438622, 438631, 438690, 438761

Abstract:

An embodiment of the invention is a metal layer of a back-end module where the height of the interconnects is greater than the height of the dielectric regions. Another embodiment of the invention is a method of fabricating a semiconductor wafer where the height of the interconnects is greater than the height of the dielectric regions.

US Patent:

7087518, Aug 8, 2006

Filed:

May 15, 2003

Appl. No.:

10/438566

Inventors:

David Gerald Farber - Wylie TX, US
William Wesley Dostalik - Plano TX, US
Robert Kraft - Plano TX, US
Andrew J. McKerrow - Dallas TX, US
Kenneth Joseph Newton - Mckinney TX, US
Ting Tsui - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/322

US Classification:

438633, 438622, 438471

Abstract:

One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

US Patent:

7112288, Sep 26, 2006

Filed:

Aug 13, 2002

Appl. No.:

10/218046

Inventors:

Fred Y. Clark - Rowlett TX, US
Andrew L. Vance - Rowlett TX, US
David G. Farber - Wylie TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/00

US Classification:

216 59, 216 60, 216 62, 216 72, 438712

Abstract:

Methods are provided for delineating different layers and interfaces for inspection of a semiconductor wafer, wherein a sectioned portion of a wafer is subjected to a reactive ion etch process before inspection using a scanning electron microscope.

US Patent:

7687407, Mar 30, 2010

Filed:

Mar 2, 2005

Appl. No.:

11/070593

Inventors:

David G. Farber - Wylie TX, US
Robert Kraft - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/302

US Classification:

438734, 216 39, 257288

Abstract:

The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion () of a substrate () to a first etch process, the first etch process designed to etch at a first entry angle (θ), and subjecting a second portion () of the substrate () to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (θ).

US Patent:

8507386, Aug 13, 2013

Filed:

Sep 13, 2010

Appl. No.:

12/880959

Inventors:

David Gerald Farber - Plano TX, US
Tom Lii - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/302

US Classification:

438719, 438727, 438739

Abstract:

A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.

US Patent:

20030170992, Sep 11, 2003

Filed:

Mar 8, 2002

Appl. No.:

10/096140

Inventors:

David Farber - Wylie TX, US
William Dostalik - Plano TX, US
Robert Kraft - Plano TX, US
Andrew McKerrow - Dallas TX, US
Kenneth Newton - Mckinney TX, US
Ting Tsui - Dallas TX, US

International Classification:

H01L021/4763
H01L021/311
H01L021/31
H01L021/469

US Classification:

438/694000, 438/778000

Abstract:

One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

US Patent:

20040169279, Sep 2, 2004

Filed:

Nov 12, 2003

Appl. No.:

10/712448

Inventors:

David Farber - Wylie TX, US
Ting Tsui - Plano TX, US
Robert Kraft - Plano TX, US
Craig Huffman - Krugerville TX, US

International Classification:

H01L023/48

US Classification:

257/750000

Abstract:

An embodiment of the invention is a metal layer of a back-end module where the height of the interconnects is greater than the height of the dielectric regions Another embodiment of the invention is a method of fabricating a semiconductor wafer where the height of the interconnects is greater than the height of the dielectric regions

US Patent:

20080268589, Oct 30, 2008

Filed:

Apr 30, 2007

Appl. No.:

11/742254

Inventors:

David Gerald Farber - Wylie TX, US
Toan Tran - Rowlett TX, US
Craig Henry Huffman - Krugerville TX, US
Brian K. Kirkpatrick - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8238
H01L 29/76

US Classification:

438218, 257369, 257E29226, 257E21632

Abstract:

The disclosure provides a method of manufacturing a semiconductor device. The method comprises forming a shallow trench isolation structure, including performing a wet etch process to remove a patterned pad oxide layer located on a semiconductor substrate. The wet etch thereby produces a divot on upper lateral edges of a insulator-filled trench in the semiconductor substrate. Forming the shallow trench isolation structure also includes forming a nitride post on a vertical wall of the divot. Forming the nitride post includes depositing a nitride layer on the insulator, and dry etching the nitride layer. The dry etch is selective towards the nitride located adjacent the vertical wall such that a portion of the nitride layer remains on the vertical wall subsequent to the dry etching.