David J Farber

US Patent:

20030078037, Apr 24, 2003

Filed:

Jul 25, 2002

Appl. No.:

10/205167

Inventors:

David Auckland - Silver Spring MD, US
Stewart Skomra - Poway CA, US
Lee Stein - Del Mar CA, US
David Farber - Landenberg PA, US

International Classification:

H04Q007/20

US Classification:

455/422000, 455/450000

Abstract:

Subscriber units and base stations of telecommunication systems are equipped with RF to IF (EXA) circuit boards which provide complete flexibility for radio communication. The boards may communicate on any air interface standard (CDMA, TDMA, Bluetooth, 3G cellular, etc.) at any frequency or band of frequencies. Separate, independent forward and reverse channels may be assignment, each having its own air interface and frequency band. When a call is initiated, a set of optimum forward and reverse channels are assigned, taking into account relevant factors such as traffic, subscriber requirements for high speed data, etc., so that the channel assignment is tailored to the current communication needs. Channel assignment is updated as needs change, as other channels become available and at handoff. In a business model, air time on multiple telecommunication systems is sold to subscribers who can use this technology to roam widely. Revenue is also generated from licensing of the EXA circuit boards in subscriber units and in base stations.

US Patent:

44930232, Jan 8, 1985

Filed:

May 22, 1981

Appl. No.:

6/266403

Inventors:

Edward S. Gavrin - Lincoln MA
Richard G. Bratt - Wayland MA
Stephen I. Schleimer - Chapel Hill NC
John F. Pilat - Raleigh NC
Michael S. Richmond - Pittsboro NC
Walter A. Wallach - Raleigh NC
Richard A. Belgard - Saratoga CA
David A. Farber - Durham NC
John K. Ahlstrom - Mountain View CA
Steven J. Wallach - Saratoga CA
Gerald F. Clancy - Saratoga CA
Craig J. Mundie - Cary NC
Thomas M. Jones - Chapel Hill NC
Brett L. Bachman - Boston MA
David H. Bernstein - Ashland MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 930

US Classification:

364200

Abstract:

A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration.

US Patent:

45162034, May 7, 1985

Filed:

Sep 11, 1981

Appl. No.:

6/302000

Inventors:

David A. Farber - Jamaica Plain MA
Brett Bachman - Shaker Heights OH
John F. Pilat - Raleigh NC
Walter A. Wallach - San Jose CA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 930

US Classification:

364200

Abstract:

Apparatus in a digital computer system for encaching data stored in the computer system's memory in a cache internal to the computer system's processor. The processor executes procedures (sequences of instructions). Data processed during an execution of a procedure is represented by operands associated with the procedure. Certain of the operands designate encacheable data items associated with each execution of the procedure. The values of the encacheable data items do not change for the duration of the execution. The operands designating encacheable data do so by means of codes specifying the designated encacheable items. The processor includes a cache for storing the encacheable items. The cache responds to a code specifying an encacheable item by outputting the value of the encacheable item specified by the code. The processor further includes cache loading apparatus for loading the encacheable items into the cache.

US Patent:

44981317, Feb 5, 1985

Filed:

May 22, 1981

Appl. No.:

6/266408

Inventors:

Richard G. Bratt - Wayland MA
Edward S. Gavrin - Lincoln MA
Stephen I. Schleimer - Chapel Hill NC
John F. Pilat - Raleigh NC
Walter A. Wallach - Raleigh NC
Michael S. Richmond - Pittsboro NC
Richard A. Belgard - Saratoga CA
David A. Farber - Durham NC
John K. Ahlstrom - Mountain View CA
Steven J. Wallach - Saratoga CA
Lawrence H. Katz - Oregon City OR
Douglas M. Wells - Chapel Hill NC
Craig J. Mundie - Cary NC
Gerald F. Clancy - Saratoga CA
David H. Bernstein - Ashland MA
Thomas M. Jones - Chapel Hill NC
Brett L. Bachman - Boston MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 922

US Classification:

364200

Abstract:

A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system utilizes unique addressing mechanisms the addresses of which have object fields, offset fields and length fields for specifying the location and the total number of bits of an addressed object. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing the user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object.

US Patent:

61856789, Feb 6, 2001

Filed:

Oct 2, 1998

Appl. No.:

9/165316

Inventors:

William A. Arbaugh - Ellicott City MD
David J. Farber - Landenberg PA
Angelos D. Keromytis - Philadelphia PA
Jonathan M. Smith - Princeton NJ

Assignee:

Trustees of the University of Pennsylvania - Philadelphia PA

International Classification:

G06F 900
G06F 1130

US Classification:

713 2

Abstract:

Integrity is rarely a valid presupposition in many systems architectures, yet it is necessary to make any security guarantees. To address this problem, the present invention discloses a secure bootstrap process, which presumes a minimal amount of integrity. The basic principle is sequencing the bootstrap process as a chain of progressively higher levels of abstraction, and requiring each layer to check a digital signature of the next layer before control is passed to it. A major design decision is the consequence of a failed integrity check. A simplistic strategy is to simply halt the bootstrap process. However, the bootstrap process of the present invention can be augmented with automated recovery procedures which preserve the security properties of the bootstrap process of the present invention under the additional assumption of the availability of a trusted repository. A variety of means by which such a repository can be implemented are disclosed with attention focused on a network-accessible repository. The recovery process is easily generalized to applications other than the bootstrap process of the present invention, such as standardized desktop management and secure automated recovery of network elements such as routers or "Active Network" elements.

US Patent:

48036196, Feb 7, 1989

Filed:

Jun 20, 1986

Appl. No.:

6/877699

Inventors:

David H. Bernstein - Ashland MA
Walter A. Wallach - Raleigh NC
Michael S. Richmond - Pittsboro NC
John K. Ahlstrom - Mountain View CA
John F. Pilat - Raleigh NC
David A. Farber - Durham NC
Richard A. Belgard - Saratoga CA
Richard G. Bratt - Wayland MA

International Classification:

G06F 1300
G06F 0900

US Classification:

364200

Abstract:

Apparatus in a digital computer system capable of performing a call operation and a return operation for obtaining addresses of data from names representing the data. Each name is permanently associated with a procedure containing instructions to which the digital computer system responds. Each name further corresponds to a name table entry which is permanently associated with the same procedure. The corresponding name table entry for a name specifies how a base address and a displacement are to be derived using a plurality of current base addresses. The values of these addresses change only when the computer system executes a call operation suspending a current execution of a procedure and commencing another current execution or a return operation terminating the current execution and resuming the execution which was suspended to commence the terminated execution. The operation of resolving a name, i. e. , obtaining the address of the data represented by the name, is performed by name interpretation apparatus in processors of the data processing system.