David N Foote

US Patent:

6380588, Apr 30, 2002

Filed:

May 9, 2000

Appl. No.:

09/567013

Inventors:

William G. En - Milpitas CA
Minh Van Ngo - Union City CA
David K. Foote - San Jose CA
Scott A. Bell - San Jose CA
Olov B. Karlsson - San Jose CA
Christopher F. Lyons - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2100

US Classification:

257345, 257327, 438595

Abstract:

A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.

US Patent:

6399480, Jun 4, 2002

Filed:

Feb 29, 2000

Appl. No.:

09/515319

Inventors:

William G. En - Sunnyvale CA
Darin A. Chan - Campbell CA
David K. Foote - San Jose CA
Fei Wang - San Jose CA
Minh Van Ngo - Union City CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 714263

US Classification:

438630, 438568, 438637, 438639, 438747

Abstract:

At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

US Patent:

6410388, Jun 25, 2002

Filed:

Jul 20, 2000

Appl. No.:

09/620480

Inventors:

George Jonathan Kluth - Sunnyvale CA
Stephen K. Park - Austin TX
Arvind Halliyal - Sunnyvale CA
David K. Foote - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438257, 438555, 438301

Abstract:

A process for fabricating a memory cell in a two-bit EEPROM device, includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with a p-type dopant, wherein the resist mask is used as an ion implant mask, and annealing the semiconductor substrate before implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the annealing of the semiconductor substrate laterally diffuses the p-type dopants to form pocket regions on either side of the EEPROM device.

US Patent:

20140034610, Feb 6, 2014

Filed:

Aug 6, 2012

Appl. No.:

13/567507

Inventors:

James P. Fazio - San Mateo CA, US
David K. Foote - San Jose CA, US
James D. Getty - Vacaville CA, US

Assignee:

NORDSON CORPORATION - Westlake OH

International Classification:

H05H 1/24
B44C 1/22

US Classification:

216 67, 15634554, 15634543

Abstract:

Apparatus and methods for plasma processing workpieces of different diameters. The apparatus includes a lift plate having an outer perimeter, an opening inside of the outer perimeter, and a gap extending between the opening and the outer perimeter. The lift plate includes annular rims of different inner diameters and that are configured to respectively support the first and second workpieces.

US Patent:

61216631, Sep 19, 2000

Filed:

Dec 18, 1997

Appl. No.:

8/992952

Inventors:

William G. En - Sunnyvale CA
Darin A. Chan - Campbell CA
David K. Foote - San Jose CA
Fei Wang - San Jose CA
Minh Van Ngo - Union City CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976
H01L 2994
H01L 31062
H01L 31113

US Classification:

257377

Abstract:

At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

US Patent:

61036110, Aug 15, 2000

Filed:

Dec 18, 1997

Appl. No.:

8/993830

Inventors:

William G. En - Milpitas CA
Minh Van Ngo - Union City CA
David K. Foote - San Jose CA
Scott A. Bell - San Jose CA
Olov B. Karlsson - San Jose CA
Christopher F. Lyons - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2100
H01L 213065

US Classification:

438595

Abstract:

Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.

US Patent:

60603933, May 9, 2000

Filed:

Dec 18, 1997

Appl. No.:

8/993888

Inventors:

Minh Van Ngo - Union City CA
Darin A. Chan - Campbell CA
David K. Foote - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21304

US Classification:

438690

Abstract:

A deposition method allows for the forming of a uniform dielectric stop layer that is substantially void of defects caused by outgassing effects. The stop layer is deposited in a reactor chamber at a higher than normal temperature of at least 480. degree. C. The stop layer is then combined with an overlying dielectric layer to provide an inter-level dielectric structure through which a local interconnect can be formed to provide a conductive path to one or more regions of the underlying semiconductor devices.

US Patent:

62075020, Mar 27, 2001

Filed:

Oct 25, 1999

Appl. No.:

9/426255

Inventors:

Kenneth Au - Fremont CA
David K. Foote - San Jose CA
Steven K. Park - Cupertino CA
Fei Wang - San Jose CA
Bharath Rangarajan - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L21/8247

US Classification:

438258

Abstract:

A process for fabricating a MONOS type Flash cell device having a periphery field oxide region and a bit-line region includes providing a semiconductor substrate and growing a barrier silicon oxide layer to overlie semiconductor substrate. Thereafter, a thick silicon nitride layer is formed to overlie the barrier silicon oxide layer. A mask and etch are performed at the periphery of the MONOS type cell to form a trench in the semiconductor substrate. The periphery field oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, a mask and etch are performed at the core of the MONOS cell to form a trench in the semiconductor substrate. The bit-line oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, the thick silicon nitride layer is removed. Since the periphery field oxide region and bit-line region are formed before the thick nitride layer is removed, the formation of an unwanted bird's beak is reduced.