David G Foote

US Patent:

6365320, Apr 2, 2002

Filed:

Jan 19, 1999

Appl. No.:

09/233849

Inventors:

David K. Foote - San Jose CA
Subhash Gupta - Singapore, SG

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03C 1725

US Classification:

4302701, 430950, 430315, 430320, 427574, 427578, 438636, 438783, 423325

Abstract:

An anti-reflective film for deep ultraviolet (DUV) photolithograghy includes silicon oxime having the formula Si N O :H , wherein x, y, and z represent the atomic percentage of nitrogen, oxygen, and hydrogen, respectively. The film is characterized by a substantial lack of bonding between silicon atoms and oxygen atoms, and has a thickness of less than approximately 600 which is selected to produce destructive interference between incident and reflected light at a selected DUV wavelength.

US Patent:

6376308, Apr 23, 2002

Filed:

Jan 19, 2000

Appl. No.:

09/487073

Inventors:

Fei Wang - San Jose CA
David K. Foote - San Jose CA
Bharath Rangarajan - Santa Clara CA
George Kluth - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218247

US Classification:

438261, 438307

Abstract:

A process for fabricating an EEPROM device having pocket substrate regions includes forming a pattern composite layer overlying a principal surface of a semiconductor substrate. The pattern composite layer includes a dielectric layer and a resist layer overlying the dielectric layer. Processing is carried out to reduce the lateral dimension of the resist layer relative to the dielectric layer thereby exposing an upper surface of the dielectric layer. A doping process is carried out in which dopants penetrate the exposed upper surface of the dielectric layer and enter the semiconductor substrate immediately below the exposed upper surface of the dielectric layer. Upon conforming the pocket regions, an oxidation process is carried out to form bit-line oxide regions in the semiconductor substrate.

US Patent:

6380588, Apr 30, 2002

Filed:

May 9, 2000

Appl. No.:

09/567013

Inventors:

William G. En - Milpitas CA
Minh Van Ngo - Union City CA
David K. Foote - San Jose CA
Scott A. Bell - San Jose CA
Olov B. Karlsson - San Jose CA
Christopher F. Lyons - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2100

US Classification:

257345, 257327, 438595

Abstract:

A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.

US Patent:

6395644, May 28, 2002

Filed:

Jan 18, 2000

Appl. No.:

09/484606

Inventors:

Dawn M. Hopper - San Jose CA
Minh Van Ngo - Fremont CA
David K. Foote - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

438738, 438199, 438299, 438216, 438287, 438744, 438735, 438791, 438952

Abstract:

A process for fabricating a semiconductor device using an ARC layer includes the formation of a silicon-rich silicon nitride material to provide an anti-reflective layer over a electrically conductive or semiconductor surface. The silicon-rich silicon nitride material is plasma deposited to provide a material having a desired refractive index, thickness uniformity, and density. The process includes the formation of a device layer on a semiconductor substrate. The device layer includes at least a silicon layer and a silicon oxide layer. A silicon-rich silicon nitride layer is formed to overlie the device layer. The silicon-rich silicon nitride material can be selectively etched, such that the silicon material and the silicon oxide material in the underlying device layer are not substantially etched.

US Patent:

6399446, Jun 4, 2002

Filed:

Oct 29, 1999

Appl. No.:

09/429722

Inventors:

Bharath Rangarajan - Santa Clara CA
David K. Foote - San Jose CA
Fei Wang - San Jose CA
Dawn M. Hopper - San Jose CA
Stephen K. Park - Austin TX
Jack Thomas - Palo Alto CA
Mark Chang - Los Altos CA
Mark Ramsbey - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218247

US Classification:

438262, 438945

Abstract:

A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H O solution.

US Patent:

6399480, Jun 4, 2002

Filed:

Feb 29, 2000

Appl. No.:

09/515319

Inventors:

William G. En - Sunnyvale CA
Darin A. Chan - Campbell CA
David K. Foote - San Jose CA
Fei Wang - San Jose CA
Minh Van Ngo - Union City CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 714263

US Classification:

438630, 438568, 438637, 438639, 438747

Abstract:

At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

US Patent:

6406960, Jun 18, 2002

Filed:

Oct 25, 1999

Appl. No.:

09/433041

Inventors:

Dawn M. Hopper - San Jose CA
David K. Foote - San Jose CA
Bharath Rangarajan - Santa Clara CA
Arvind Halliyal - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218247

US Classification:

438261, 438763, 438954

Abstract:

A process for fabricating an ONO layer in a non-volatile memory device including the steps of forming a first silicon oxide layer, a silicon-rich silicon nitride layer and a second silicon oxide layer. The silicon-rich silicon nitride layer is formed by either a PECVD process, an LPCVD, or an RTCVD process. The silicon-rich silicon nitride layer effectively holds electrical charge making the ONO layer particularly useful as a floating gate electrode in a two-bit EEPROM device.

US Patent:

6410388, Jun 25, 2002

Filed:

Jul 20, 2000

Appl. No.:

09/620480

Inventors:

George Jonathan Kluth - Sunnyvale CA
Stephen K. Park - Austin TX
Arvind Halliyal - Sunnyvale CA
David K. Foote - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438257, 438555, 438301

Abstract:

A process for fabricating a memory cell in a two-bit EEPROM device, includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with a p-type dopant, wherein the resist mask is used as an ion implant mask, and annealing the semiconductor substrate before implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the annealing of the semiconductor substrate laterally diffuses the p-type dopants to form pocket regions on either side of the EEPROM device.