David S Francis

US Patent:

57847002, Jul 21, 1998

Filed:

May 2, 1996

Appl. No.:

8/641820

Inventors:

Chein C. Chen - Sugar Land TX
John C. Cooper - Houston TX
David E. Francis - Houston TX
Joseph A. Coomes - Missouri City TX
Jerald G. Leach - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1206

US Classification:

711172

Abstract:

A memory interface unit capable of coupling a microprocessor to memory external to the microprocessor, wherein the memory can be of at least two types differing in width, and where the data stored in such memory can be in different sizes, and wherein the memory can be formed in sections. The invention utilizes means for controlling at least two strobe signal lines and means for shifting the memory address lines, programmably, so as to accommodate the various combinations of memory width and data size.

US Patent:

57614784, Jun 2, 1998

Filed:

May 24, 1996

Appl. No.:

8/653220

Inventors:

Chein C. Chen - Sugar Land TX
John C. Cooper - Houston TX
David E. Francis - Houston TX
Joseph A. Coomes - Missouri City TX
Jerald G. Leach - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1202

US Classification:

39549703

Abstract:

A memory interface unit for coupling a microprocessor to a memory external to the microprocessor, the memory being utilized for the storage of data therein and the retrieval of data therefrom, and the memory being provided in one or more memory banks, each of the banks being provided with a set of address lines and a byte enable line, data being transferring to and from each of the memory banks on a group of data lines, and the memory banks being provided in one or more banks whereby the group or groups of data lines, as the case may be, provide a memory data path having a physical transfer width for transfer of data to and from the memory, and the data being stored and retrieved over the memory data path in two or more data types, each type having a different size, the memory interface unit being provided with a set of address pins and a set of strobe pins, comprising. The unit includes a first element for providing an indication of a physical transfer width of a memory coupled to the memory interface unit. Also provided is a second element for providing an indication of a data type to be transferred to or from the memory.