David D French

US Patent:

7809975, Oct 5, 2010

Filed:

Mar 29, 2007

Appl. No.:

11/729728

Inventors:

David French - Grafton MA, US
Douglas Sullivan - Hopkinton MA, US
William Buckley - Brighton MA, US
Alex Sanville - Boxborough MA, US
Phillip J. Manning - East Geenwich RI, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 11/00

US Classification:

714 3

Abstract:

A computerized system includes two storage processors having respective local write caches configured to mirror each other. When a first storage processor becomes unavailable and mirroring of the local write caches is prevented, the computerized system continues to attend to write operations from an external host in a write-back manner by caching write data from the write operations in the local write cache of the second storage processor. In response to a failure of the second storage processor, the computerized system preserves the write data within the local write cache of the second storage processor. Then, upon recovery of the second storage processor from the failure, the computerized system continues to attend to further write operations from the external host in the write-back manner by caching additional write data in the local write cache of the second storage processor while the first storage processor remains unavailable.

US Patent:

7849350, Dec 7, 2010

Filed:

Sep 28, 2006

Appl. No.:

11/529124

Inventors:

David French - Grafton MA, US
Douglas Sullivan - Hopkinton MA, US
Bill Buckley - Brighton MA, US
Matt Yellen - Worcester MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 11/00

US Classification:

714 3

Abstract:

A technique responds to a storage processor failure. The technique involves performing write-back caching operations using a cache of a first storage processor, and mirroring data from the cache of the first storage processor to a cache of a second storage processor. The technique further involves, after of a failure of the second storage processor in which the second storage processor becomes unavailable, continuing to perform write-back caching operations using the cache of the first storage processor while the second storage processor remains unavailable. A cache controller is capable of being modified so that any write data in the cache of the first storage processor persists if the first storage processor encounters a failure thus preventing loss of the cached write data.