David C Gilmer

Address:

5208 Mcdade Dr, Austin, TX 78735

VIN:

2A8GP64L57R157470

Make:

CHRYSLER

Model:

TOWN AND COUNTRY

Year:

2007

US Patent:

6573160, Jun 3, 2003

Filed:

May 26, 2000

Appl. No.:

09/578404

Inventors:

Marius Orlowski - Austin TX
David C. Gilmer - Austin TX
Prasad V. Alluri - Round Rock TX
Christopher C. Hobbs - Austin TX
Michael J. Rendon - Austin TX
Iuval R. Clejan - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2120

US Classification:

438480, 438198, 438583

Abstract:

Techniques for forming gate dielectric layers ( ) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions ( ) are formed prior to formation of structures included in the gate structure ( ) of the semiconductor device, where the gate structures ( ) are preferably formed using low temperature operations that allow the amorphous silicon regions ( ) to remain in an amorphous state. Source/drain regions ( ) are formed in the amorphous silicon regions ( ), and then the substrate is annealed to recrystallize the amorphous regions.

US Patent:

6717226, Apr 6, 2004

Filed:

Mar 15, 2002

Appl. No.:

10/098706

Inventors:

Rama I. Hegde - Austin TX
Joe Mogab - Austin TX
Philip J. Tobin - Austin TX
Hsing H. Tseng - Austin TX
Chun-Li Liu - Mesa AZ
Leonard J. Borucki - Mesa AZ
Tushar P. Merchant - Gilbert AZ
Christopher C. Hobbs - Austin TX
David C. Gilmer - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2976

US Classification:

257406, 257410, 257411, 438216, 438261, 438591

Abstract:

A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.

US Patent:

6787421, Sep 7, 2004

Filed:

Aug 15, 2002

Appl. No.:

10/219522

Inventors:

David C. Gilmer - Austin TX
Christopher C. Hobbs - Austin TX

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 218234

US Classification:

438275, 438287, 438981

Abstract:

A semiconductor device ( ) having two different gate dielectric thicknesses is formed using a single high-k dielectric layer, preferably a metal oxide. A thicker first gate dielectric ( ) is formed in a region of the device for higher voltage requirements, e. g. an I/O region ( ). A thinner second gate dielectric ( ) is formed in a region of the device for lower voltage requirements, e. g. a core device region ( ). First and second dielectrics are preferably silicon dioxide or oxynitride. A metal oxide ( ) is deposited over both dielectrics, followed by deposition of a gate electrode material ( ). By using a single metal oxide layer in forming the gate dielectric stack for each transistor, together with high quality silicon dioxide or oxynitride dielectric layers, problems associated with selective etching of the metal oxide may be avoided, as may problems associated with various interfaces between the metal oxide and damaged or treated surfaces.

US Patent:

6972224, Dec 6, 2005

Filed:

Mar 27, 2003

Appl. No.:

10/400896

Inventors:

David C. Gilmer - Austin TX, US
Srikanth B. Samavedam - Austin TX, US
Philip J. Tobin - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L021/8238

US Classification:

438199, 438216, 438279, 438585

Abstract:

A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (), such as HfO, is deposited on a semiconductor substrate. A sacrificial layer (), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area () of the substrate is exposed and gate dielectric over a second (nMOS, for example) area () of the substrate continues to be protected by the sacrificial layer. A first gate conductor material () is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

US Patent:

7015153, Mar 21, 2006

Filed:

Oct 20, 2004

Appl. No.:

10/969634

Inventors:

Dina H. Triyoso - Austin TX, US
Olubunmi O. Adetutu - Austin TX, US
David C. Gilmer - Austin TX, US
Darrell Roan - Austin TX, US
James K. Schaeffer - Austin TX, US
Philip J. Tobin - Austin TX, US
Hsing H. Tseng - Austin TX, US

Assignee:

Freescale Semiconductor, inc. - Austin TX

International Classification:

H01L 21/31

US Classification:

438785, 438778

Abstract:

A method for forming at least a portion of a semiconductor device includes providing a semiconductor substrate, flowing a first precursor gas over the substrate to form a first metal-containing layer overlying the semiconductor substrate, and after completing said step of flowing the first precursor gas, flowing a first deuterium-containing purging gas over the first metal-containing layer to incorporate deuterium into the first metal-containing layer and to also purge the first precursor gas. The method may further include flowing a second precursor gas over the first metal-containing layer to react with the first metal-containing layer to form a metal compound-containing layer, and flowing a second deuterium-containing purging gas over the metal compound-containing layer to incorporate deuterium into the metal compound-containing layer and to also purge the second precursor gas.

US Patent:

7297588, Nov 20, 2007

Filed:

Jan 28, 2005

Appl. No.:

11/046079

Inventors:

Olubunmi O. Adetutu - Austin TX, US
David C. Gilmer - Austin TX, US
Philip J. Tobin - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/8238

US Classification:

438229, 438659, 257E21637

Abstract:

One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

US Patent:

7432164, Oct 7, 2008

Filed:

Jan 27, 2006

Appl. No.:

11/342025

Inventors:

Olubunmi O. Adetutu - Austin TX, US
David C. Gilmer - Austin TX, US
Philip J. Tobin - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/8236
H01L 21/336
H01L 21/8234

US Classification:

438276, 438289, 438290, 438275, 257E2916, 257E21151, 257E21623

Abstract:

A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.

US Patent:

7655550, Feb 2, 2010

Filed:

Jun 30, 2006

Appl. No.:

11/427980

Inventors:

James K. Schaeffer - Austin TX, US
David C. Gilmer - Austin TX, US
Mark V. Raymond - Austin TX, US
Philip J. Tobin - Austin TX, US
Srikanth B. Samavedam - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/4763

US Classification:

438592, 438591, 438257, 257310, 257407

Abstract:

A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.