David R Gonzales

Address:

9912 Wier Loop Cir, Austin, TX 78736

VIN:

5TBRU54147S449967

Make:

TOYOTA

Model:

TUNDRA

Year:

2007

Address:

6500 Champion Grandview Way APT 420, Austin, TX 78750

VIN:

1GCHK23657F531789

Make:

CHEVROLET

Model:

SILVERADO 2500HD

Year:

2007

Address:

12025 Buzz Schneider Ln, Austin, TX 78748

VIN:

2GCEC13V371173231

Make:

Chevrolet

Model:

Silverado 1500 Classic

Year:

2007

US Patent:

6748558, Jun 8, 2004

Filed:

May 10, 2000

Appl. No.:

09/567973

Inventors:

David R. Gonzales - Austin TX
Brian D. Branson - Austin TX
Jimmy Gumulja - Austin TX
William C. Moyer - Dripping Springs TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1100

US Classification:

714 47, 702182

Abstract:

A performance monitor system includes a core processor ( ), a core processor associated device, such as a cache ( ), and first logic, such as performance logic ( ). The core processor ( ) is operable to execute information. The core processor associated device provides a first signal (CACHE_PERF), which defines performance of the core processor associated device ( ) during operation of the core processor ( ). The first logic ( ) is coupled to the core processor associated device ( ) and monitors the first signal (CACHE_PERF) in response to a second signal (WPT ), which defines a match of user-settable attributes associated with the operation of the core processor ( ).

US Patent:

61451223, Nov 7, 2000

Filed:

Apr 27, 1998

Appl. No.:

9/067102

Inventors:

Gary Lynn Miller - Round Rock TX
David Ruimy Gonzales - Austin TX
Gary Lee Whisenhunt - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 945

US Classification:

717 4

Abstract:

In one embodiment, a development interface (14) for a data processor (10) includes development registers (39), auxiliary pin interface and control (32), auxiliary pins (31), and a JTAG controller (4)).

US Patent:

54886880, Jan 30, 1996

Filed:

Mar 30, 1994

Appl. No.:

8/220329

Inventors:

David R. Gonzales - Austin TX
Gordon A. Carichner - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1134

US Classification:

3951831

Abstract:

A data processor (20) includes a diagnostic circuit (23) with a first-in, first-out memory (FIFO) (25) for storing sequential states of an internal bus, such as a program address bus. In one mode, the diagnostic circuit (23) halts a central processing unit (CPU) (21) and the FIFO (25) on the occurrence of an event condition, such as a hardware breakpoint. In a second mode, the diagnostic circuit (23) halts the FIFO (25) but keeps the CPU (21) in normal operation. Thus, the contents of the FIFO (25) may be examined through a serial port while the CPU (21) is executing instructions normally.