David I Grant

US Patent:

6348780, Feb 19, 2002

Filed:

Sep 22, 2000

Appl. No.:

09/668842

Inventors:

David Grant - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 110

US Classification:

323222, 323286, 323284

Abstract:

A power converter is comprised of a hysteretic controller including a feedback circuit that monitors the output frequency of the controller, compares it to a reference generated either internally or externally by the user, and then adjusts the hysteresis of the controller accordingly. The adjusted hysteresis levels will then cause the switching frequency to either increase or decrease thereby controlling the switching frequency of the power supply controller and maintaining it at a desired level.

US Patent:

6465898, Oct 15, 2002

Filed:

Jul 23, 2001

Appl. No.:

09/911557

Inventors:

Laura A. Hnilo - McKinney TX
Mike P. Pierce - Plano TX
Roy A. Hastings - Allen TX
David Grant - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23544

US Classification:

257797, 257734, 257798

Abstract:

A semiconductor chip bearing an alignment mark, particularly useful for wire bonder alignment on chips having bonding surfaces over the active circuits. The marks are fabricated on diagonal corners of the chip, and each mark consists of a pair of touching squares which are rotated about 90 degrees from each other in the opposite chip corners. The unique positioning of the marks, as well as the rotation provides both gross chip position features useful in mounting the chip on a lead frame, as well as fine alignment set-up or teaching aids for wire bonding. The small, high visual contrast features of the alignment mark are fabricated simultaneously with the top active metallization of the IC chip, and are not covered by passivation coating or additional metal layers.

US Patent:

6535055, Mar 18, 2003

Filed:

Mar 14, 2002

Appl. No.:

10/097976

Inventors:

John C. Teel - Plano TX
David Grant - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 110

US Classification:

327540

Abstract:

The leakage current correction circuit uses a dummy device Mleak to detect leakage current. The dummy device is a scaled down version of the pass element Mpass. A current router is used to either gain up the dummy leakage current and apply it to the output Vout or simply dump the small un-gained current to ground GND.

US Patent:

6661216, Dec 9, 2003

Filed:

Aug 26, 2002

Appl. No.:

10/227942

Inventors:

David A. Grant - Dallas TX
David D. Briggs - Richardson TX
Ayesha I. Mayhugh - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 158

US Classification:

323282, 323285, 323901

Abstract:

An apparatus for presenting a regulated output at an output locus established at a precharge level includes: (a) an error indicator generating an error signal indicating difference between a reference signal and a sensed signal; (b) a pulse indicator coupled with the error indicator generating a pulse signal indicating difference between the error signal and a periodic signal; (c) a switching device responding to the pulse signal effecting coupling of the output locus with a first terminal or a second terminal depending upon whether the pulse signal is at a first level or a second level; and (d) a driver controller coupled with the pulse indicator and the switching device that provides a control signal to the switching device indicating at least one characteristic of the pulse signal. The switching device is operative or inoperative depending upon whether the control signal is in a first state or a second state.

US Patent:

6709900, Mar 23, 2004

Filed:

Jun 11, 2002

Appl. No.:

10/166964

Inventors:

Taylor R. Efland - Richardson TX
David A. Grant - Dallas TX
Ramanathan Ramani - Richardson TX
Dale Skelton - Plano TX
David D. Briggs - Richardson TX
Chin-Yu Tsai - HsinChu Hsien, TW

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21332

US Classification:

438140, 438141, 438454

Abstract:

A power integrated circuit architecture ( ) having a high side transistor ( ) interposed between a control circuit ( ) and a low side transistor ( ) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region ( ) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring ( ) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays ( ) partitioned by at least one deep n-type region ( ), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.

US Patent:

6710427, Mar 23, 2004

Filed:

Jun 11, 2002

Appl. No.:

10/167136

Inventors:

Taylor R. Efland - Richardson TX
David A. Grant - Dallas TX
Ramanathan Ramani - Richardson TX
Chin-Yu Tsai - HsinChu Seien, TW
David D. Briggs - Richardson TX
Dale Skelton - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2900

US Classification:

257549, 257502, 257500, 257544

Abstract:

A distributed power device ( ) including a plurality of tank regions ( ) separated from one another by a deep n-type region ( ), and having formed in each tank region a plurality of transistors ( ). The plurality of transistors ( ) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D ) is defined from each tank region to a buried layer, and a second parasitic diode (D ) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer ( ) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D ) between the NBL layer and the substrate will never be forward biased.

US Patent:

6727752, Apr 27, 2004

Filed:

May 29, 2002

Appl. No.:

10/156926

Inventors:

David L. Skinner - Dallas TX
Wayne Tien-Feng Chen - Plano TX
David A. Grant - Dallas TX
Vadim Ivanov - Tucson AZ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 3217

US Classification:

330251, 330207 A

Abstract:

A modulation scheme can drive an associated load that is coupled between a pair of outputs by providing a switching signal at one of the outputs and a non-switching signal at the other output independent of the direction of current relative to the respective outputs. Because switching occurs only at one of the outputs in this mode of operation, a single filter can be used to mitigate switching noise at the switching output. Another aspect relates to another mode of operation in which one or both of the outputs can be controlled to operate linearly, such as during a zero crossing condition, so as to help reduce crossover distortion.

US Patent:

6744243, Jun 1, 2004

Filed:

Jun 28, 2001

Appl. No.:

09/895959

Inventors:

David G. Daniels - Dallas TX
Dale J. Skelton - Plano TX
Ayesha I. Mayhugh - Richardson TX
David A. Grant - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 144

US Classification:

323284, 323280

Abstract:

A low gain feedback compensation circuit is provided on an integrated circuit. The feedback compensation circuit is coupled to a step down power supply on the integrated circuit. The step down power supply is operable to receive an input voltage and to generate an output voltage based on the input voltage. The feedback compensation circuit includes a line regulation circuit. The line regulation circuit is operable to receive the input voltage and a reference voltage. The line regulation circuit is also operable to generate an offset voltage based on the input voltage and the reference voltage.

Address:

6300 Caroline Dr, Frisco, TX 75034

Phone:

(972)2945838

VIN:

5UXFE43508L023863

Make:

BMW

Model:

X5

Year:

2008

Address:

5860 Baker Dr, The Colony, TX 75056

VIN:

1N6BA07A67N215459

Make:

NISSAN

Model:

TITAN

Year:

2007