David Allen Guidry

US Patent:

7265694, Sep 4, 2007

Filed:

Mar 25, 2004

Appl. No.:

10/808908

Inventors:

David Walker Guidry - Rowlett TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 1/10

US Classification:

341120, 341158, 324 7615

Abstract:

A system and method for providing successive approximation, such as can be used by a successive approximation converter or by a coherent undersampling digitizer. The system comprising a memory having a successive approximation value and a comparison system configured to receive and amplify the difference between a test signal and the successive approximation value and to convert the amplified signal to a digital signal. A multi-bit analog to digital convert can be used to convert the amplified signal to a digital signal.

US Patent:

8130032, Mar 6, 2012

Filed:

Sep 29, 2010

Appl. No.:

12/893346

Inventors:

Dale Alan Heaton - Lucas TX, US
David Walker Guidry - Rowlett TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 19/00

US Classification:

330 2, 330 69

Abstract:

The invention relates to systems and methods for high-sensitivity detection of input bias current. The invention more particularly relates to platforms and techniques for the calibration and measurement of input bias current in op amps or other devices. In embodiments, the platform can incorporate a servo loop connected to a high-sensitivity test amplifier, such as an instrumentation amplifier. The test amplifier can complete a switchable circuit with the servo loop and detect a calibration input bias current for the test platform, without a production device in place. The device under test can be switched into the servo loop, and the total bias current measured with both the device under test and test amplifier in-circuit. The difference between the measured current with the device inserted and the previously measured calibration current represents the bias current for the subject device, without attaching external meters or requiring reference parts of the production type.

US Patent:

7363568, Apr 22, 2008

Filed:

Nov 3, 2004

Appl. No.:

10/979981

Inventors:

David Walker Guidry - Rowlett TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 11/00

US Classification:

714745, 714 47

Abstract:

System and method for testing differential signal crossover in high-speed electronic equipment. A preferred embodiment comprises a test circuit coupled to a device under test (DUT) and an automatic test equipment (ATE). The test circuit comprises a pair of window comparators coupled to a differential mode signal from the DUT, each window comparator configured to compare one of two signals making up the differential mode signal with a voltage boundary when enabled by an enable signal. The ATE is configured to provide clock signals to the test circuit and the DUT and to process data produced by the test circuit to determine if the differential signal crossover meets timing constraints. The test circuit uses undersampling to enable testing of high frequency signals without requiring an extremely high sampling rate.

US Patent:

20030229658, Dec 11, 2003

Filed:

Jun 6, 2002

Appl. No.:

10/162677

Inventors:

David Guidry - Dallas TX, US

International Classification:

G06F001/02

US Classification:

708/272000

Abstract:

A sin (x) or cos (x) computational generator is provided by a coarse and fine storage element sharing a common address bus with the coarse storage element storing full precision values for every Jsample and said fine storage element storing correction values between the Jsamples. An arithmetic block operates on the output of the storage elements in response to addresses on the address bus to provide full precision values without storing full precision values.

US Patent:

20050229064, Oct 13, 2005

Filed:

Apr 12, 2004

Appl. No.:

10/822415

Inventors:

David Guidry - Rowlett TX, US

International Classification:

G01R031/28
G06F011/00

US Classification:

714742000

Abstract:

Methods and systems for digital testing of semiconductor devices are disclosed. The inventions include testing modules () for use with automatic test equipment (ATE) and device interface boards () in order to extend their capabilities to perform digital testing of semiconductor devices (). Testing modules () disclosed include memory () and a test engine (), which may be configured for digital testing according to further steps of the invention.

US Patent:

20060001562, Jan 5, 2006

Filed:

Jun 30, 2004

Appl. No.:

10/881576

Inventors:

David Guidry - Rowlett TX, US
Sasikumar Cherubal - Richardson TX, US

International Classification:

H03M 1/12

US Classification:

341155000

Abstract:

According to one embodiment of the invention, a method of sampling a signal is provided. The method includes receiving over a signal path an analog signal generated using a first clock signal by a first device. The method also includes sampling the analog signal using a second clock signal to generate a numeric representation of at least a portion of the analog signal. The frequencies of the first and the second clock signals differ from one another by a known amount. The method also includes communicating over the signal path the numeric representation for receipt by a second device. The signal path experiences loading and at least a majority of the loading of the signal path occurs between the sampler and the second device.

US Patent:

20060061349, Mar 23, 2006

Filed:

Sep 22, 2004

Appl. No.:

10/946661

Inventors:

David Guidry - Rowlett TX, US

International Classification:

G01R 13/02

US Classification:

324076470

Abstract:

The present invention provides a system () that overcomes performance incongruities between a high-speed device () and commercial ATE (). The system of the present invention provides an analog-to-analog sampler (), having a clock input (). The analog-to-analog sampler receives a first analog test signal () from the high-speed device, and converts it into a second analog test signal () at a desired rate, utilizing an analog-to-digital-to-analog conversion function () and a decimation function (). The ATE system houses an analog capture component (). The analog capture component has a clock input (), and receives the second analog test signal for conversion into digital format. A series of clock signals () are generated from a common frequency reference source (), to provide the necessary clock signals throughout the system.

US Patent:

20130014983, Jan 17, 2013

Filed:

Jul 14, 2011

Appl. No.:

13/182795

Inventors:

Michael Patrick Korson - Plano TX, US
David Walker Guidry - Rowlett TX, US

International Classification:

H05K 9/00

US Classification:

174378, 174377

Abstract:

An apparatus includes a device contactor having an integrated radio frequency (“RF”) shield and a gasket coupled to a first surface of the device contactor. When the device contactor is removably attached to a printed circuit board (“PCB”), the gasket contacts the PCB, and the RF shield and the gasket form a Faraday cage that shields a device under test and/or circuitry associated with the device under test from RF noise.